Dynamic storage allocation in a logic analyzer

• US 5,347,540 A
• Filed: 07/08/1992
• Issued: 09/13/1994
• Est. Priority Date: 07/08/1992
• Status: Expired due to Fees

• Current Assignee: Tektronix Incorporated (Fortive Corp.)
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Karrick, Kevin C.
• Primary Examiner(s): Chin, Stephen
• Application Number:
  US07/910,059
• Time in Patent Office: 797 Days
• Field of Search: 375/25, 375/10, 375/114, 375/116, 375/117, 370/43, 370/48, 370/99, 370/100, 340/825.14
• US Class Current: 375/224
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/25 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware

Abstract

An apparatus and method for dynamic memory allocation conserves memory resources while providing efficient and effective interaction between concurrent synchronous and asynchronous acquisition of data for logic analysis. The apparatus includes circuitry for acquiring synchronous data, circuitry for acquiring asynchronous data, circuitry for generating timestamp values, circuitry for determining when the synchronous data is valid, circuitry for determining when the asynchronous data is valid, and circuitry for packing valid synchronous data and valid asynchronous data into a memory according to the sequence in which it was acquired with sufficient timestamp values included to permit reconstruction of the relative timing between all of the acquired data, with each data and timestamp value being identified with status bits to indicate whether it was synchronous data, asynchronous data, or a timestamp value. The method of dynamic memory allocation includes the steps of acquiring synchronous data, acquiring asynchronous data, generating timestamp values, determining when the synchronous data is valid, also determining when the asynchronous data is valid, and packing valid synchronous data and valid asynchronous data into a memory according to the sequence in which it was acquired with sufficient timestamp values included to permit reconstruction of the relative timing between all of the acquired data, with each data and timestamp value being identified with status bits to indicate whether it was synchronous data, asynchronous data, or a timestamp value.

Claims

1. A method of dynamic memory allocation between synchronous and asynchronous data acquired by a test instrument for digital data acquisition and analysis, the method comprising the steps of:

acquiring synchronous data from a first input signal source at times determined by a clock source external to the test instrument;

acquiring asynchronous data from a second input signal source at times determined by a clock source internal to the test instrument;

generating timestamp values;

determining by reference to the clock source external to the test instrument when the synchronous data is valid;

determining when the asynchronous data is valid; and

packing valid synchronous data, valid asynchronous data, and timestamp values into a memory according to a sequence in which the synchronous data and asynchronous data was acquired, with each data and timestamp value being identified with status bits to indicate which was synchronous data, which was asynchronous data, and which was a timestamp value.

3. A method according to claim 1 wherein the second input signal source is the same as the first input signal source.

5. A method according to claim 1 wherein the packing step comprises the steps of:

associating timestamp values with stored data when a data acquisition rate permits; and

storing data without timestamp values when the data acquisition rate causes data acquisition to occur at a maximum rate.

2. An apparatus for dynamically allocating memory space between synchronous and asynchronous data acquired by a test instrument for digital data acquisition and analysis comprising:

means for acquiring synchronous data from a first input signal source at times determined by a clock source external to the test instrument;

means for acquiring asynchronous data from a second input signal source at times determined by a clock source internal to the test instrument;

means for generating timestamp values;

mean for determining by reference to the clock source external to the test instrument when the synchronous data is valid to produce valid synchronous data;

mean for determining when the asynchronous data is valid to produce valid asynchronous data; and

means for packing the valid synchronous data, the valid asynchronous data, and the timestamp values into a memory according to a sequence in which the synchronous data and asynchronous data was acquired, with each data and timestamp value being identified with status bits to indicate which was synchronous data, which was asynchronous data, and which was a timestamp value.

4. An apparatus according to claim 2 wherein the second input signal source is the same as the second input signal source.

6. An apparatus according to claim 2 wherein the means for packing associates timestamp values with stored data when a data acquisition rate permits and stores the data without timestamp values when the data acquisition rate is maximum.