High current high voltage vertical PMOS in ultra high voltage CMOS
First Claim
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1. A vertical transistor comprising:
- a) a substrate of a given first carrier type having an upper area and a lower area,b) at least one combination gate/source area with a center wherein said combination gate/source area comprises a well region of a second carrier type, a source region of said first carrier type, first and second gate regions of said second carrier type, and first and second pinchoff regions of said first carrier type, wherein;
i) said first pinchoff region is in the center,ii) said first gate region is adjacent to and surrounds said first pinchoff region,iii) said source region is adjacent to and surrounds said first gate region,iv) said second gate region is adjacent to and surrounds said source region,v) said second pinchoff region is adjacent to and surrounds said second gate region, andvi) said well region extends underneath said source region and said first and second gate regions and extends at least partially underneath said first and second pinchoff regions,c) a drain area,d) said combination gate/source area built in the upper area of said substrate such that the remaining lower portion of said substrate underneath said combination gate/source area is said drain area.
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Abstract
A vertical transistor which is built in a substrate of a given first carrier type utilizing standard processes but which has a unique layout which facilitates high voltage, high current operation while still conserving space. The transistor is built utilizing a repeatable combination gate/source area that is built in the upper area of the substrate such that the remaining lower portion of the substrate underneath the combination gate/source area is the drain area of the transistor.
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Citations
5 Claims
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1. A vertical transistor comprising:
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a) a substrate of a given first carrier type having an upper area and a lower area, b) at least one combination gate/source area with a center wherein said combination gate/source area comprises a well region of a second carrier type, a source region of said first carrier type, first and second gate regions of said second carrier type, and first and second pinchoff regions of said first carrier type, wherein; i) said first pinchoff region is in the center, ii) said first gate region is adjacent to and surrounds said first pinchoff region, iii) said source region is adjacent to and surrounds said first gate region, iv) said second gate region is adjacent to and surrounds said source region, v) said second pinchoff region is adjacent to and surrounds said second gate region, and vi) said well region extends underneath said source region and said first and second gate regions and extends at least partially underneath said first and second pinchoff regions, c) a drain area, d) said combination gate/source area built in the upper area of said substrate such that the remaining lower portion of said substrate underneath said combination gate/source area is said drain area. - View Dependent Claims (2, 3, 4, 5)
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Specification