High current high voltage vertical PMOS in ultra high voltage CMOS

• US 5,349,223 A
• Filed: 12/14/1993
• Issued: 09/20/1994
• Est. Priority Date: 12/14/1993
• Status: Expired due to Fees

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Buhler, Steven A., Vo, Tuan A., Mojaradi, Mohamad M.
• Primary Examiner(s): CARROLL, JAMES J
• Application Number:
  US08/166,400
• Time in Patent Office: 280 Days
• Field of Search: 257/329, 257/331, 257/334, 257/335, 257/337, 257/339, 257/340, 257/341, 257/343, 257/629, 257/630
• US Class Current: 257/329
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors

Abstract

A vertical transistor which is built in a substrate of a given first carrier type utilizing standard processes but which has a unique layout which facilitates high voltage, high current operation while still conserving space. The transistor is built utilizing a repeatable combination gate/source area that is built in the upper area of the substrate such that the remaining lower portion of the substrate underneath the combination gate/source area is the drain area of the transistor.

Claims

1. A vertical transistor comprising:

a) a substrate of a given first carrier type having an upper area and a lower area,

b) at least one combination gate/source area with a center wherein said combination gate/source area comprises a well region of a second carrier type, a source region of said first carrier type, first and second gate regions of said second carrier type, and first and second pinchoff regions of said first carrier type, wherein;

i) said first pinchoff region is in the center,

ii) said first gate region is adjacent to and surrounds said first pinchoff region,

iii) said source region is adjacent to and surrounds said first gate region,

iv) said second gate region is adjacent to and surrounds said source region,

v) said second pinchoff region is adjacent to and surrounds said second gate region, and

vi) said well region extends underneath said source region and said first and second gate regions and extends at least partially underneath said first and second pinchoff regions,

c) a drain area,

d) said combination gate/source area built in the upper area of said substrate such that the remaining lower portion of said substrate underneath said combination gate/source area is said drain area.

2. The vertical transistor of claim 1 further comprising a second combination gate/source area surrounding said first combination gate/source area:

a) a first pinchoff region of the second combination gate/source area is adjacent to and surrounds the second pinchoff region of the first combination gate/source area,

b) a first gate region of the second combination gate source/area is adjacent to and surrounds said first pinchoff region of the second combination gate source/area,

c) a source region of the second combination gate source/area is adjacent to and surround said first gate region of the second combination gate source/area,

d) a second gate region of the second combination gate source/area is adjacent to and surrounds said source region of the second combination gate source/area,

e) a second pinchoff region of the second combination gate source/area is adjacent to and surrounds said second gate region of the second combination gate source/area,

f) a well region of said second combination gate/source area extends underneath said source region and said first and second gate regions of said second combination gate/source area and extends at least partially underneath said first and second pinchoff regions of said second combination gate/source area, and

g) a first and second combination gate/source areas are built in the upper area of said substrate such that the remaining lower portion of said substrate underneath said first and second combination gate/source areas is said drain area.

3. The vertical transistor of claim 1 wherein said surrounding areas are annular.

4. The vertical transistor of claim 3 wherein said annular surrounding areas are circular.

5. The vertical transistor of claim 1 further comprising:

a) a pinchoff contact area of a given second carrier type adjacent to and surrounding said second pinchoff area,

b) a field plate area adjacent to and surrounding said pinchoff contact area,

c) a field oxide area substantially underneath said field plate area,

d) a third pinchoff area, of a given second carrier type, substantially underneath said field oxide area, and

e) a drain contact area, of a first carrier type, adjacent to and surrounding said field plate area.