Integrable MOS and IGBT devices having trench gate structure

• US 5,349,224 A
• Filed: 06/30/1993
• Issued: 09/20/1994
• Est. Priority Date: 06/30/1993
• Status: Expired due to Fees

• Current Assignee: Purdue Research Foundation (Purdue University)
• Original Assignee: Purdue Research Foundation (Purdue University)
• Inventors: Gilbert, Percy V., Neudeck, Gerold W.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/085,845
• Time in Patent Office: 447 Days
• Field of Search: 257/333, 257/341, 257/378, 257/397, 257/401, 257/577, 437/40, 437/67, 437/90, 437/203, 437/225, 437/913
• US Class Current: 257/333
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66325 controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7398 with both emitter and collector contacts in the same substrate side
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

A power semiconductor device which is integrable in an integrated circuit includes a semiconductor body having first and second major opposing surfaces with a first doped region of a first conductivity type therebetween, second and third doped regions of a second conductivity type formed in the first doped region, the second and third doped regions being spaced apart and abutting the first surface, and fourth and fifth doped regions of the first conductivity type respectively formed in the second and third doped regions and abutting the first surface. Sixth and seventh doped regions extend from the first surface into the first region, the sixth region being adjacent to the second and fourth regions and spaced therefrom by an electrically insulative layer, the seventh region being adjacent to the third and fifth regions and spaced therefrom by an insulative layer. The first doped region extends toward the first surface between the sixth and seventh regions and separated therefrom by an electrically insulative layer of variable thickness suitable for voltage blocking. An eighth doped region in the first doped region between the sixth and seventh regions abuts the first surface and forms the drain of a MOSFET or the anode of an IGBT. In fabricating the device, reactive ion etching is used to from a trench in which the sixth and seventh regions are formed. The trench is filled by epitaxially grown semiconductor material in which the eighth doped region is formed. The fourth and fifth doped regions form the source of a MOSFET or a cathode of an IGBT. All ohmic contacts to the device can be made on the first surface.

Claims

1. A power semiconductor device which is integrable in an integrated circuit comprising

a semiconductor body having first and second major opposing surfaces with a first doped region of a first conductivity type therebetween,

second and third doped regions of a second conductivity type formed in said first doped region, said second and third doped regions being spaced apart and abutting said first surface,

fourth and fifth doped regions of said first conductivity type respectively formed in said second and third doped regions and abutting said first surface,

sixth and seventh doped regions extending from said first surface into said first region, said sixth region being adjacent to said second and fourth regions and spaced therefrom by an electrically insulative gate layer, said seventh region being adjacent to said third and fifth regions and spaced therefrom by an electrically insulative gate layer,

said first doped region extending toward said first surface between said sixth and seventh regions and separated from said sixth and seventh regions by an electrically insulative layer of suitable thickness for voltage blocking, and

an eighth doped region in said first doped region between said sixth and seventh regions and abutting said first surface.

2. The power semiconductor device as defined by claim 1 and further including

an ohmic contact to said second and fourth regions,

an ohmic contact to said third and fifth regions, and

an ohmic contact to said sixth and seventh regions.

3. The power semiconductor device as defined by claim 1 wherein said eighth doped region is of said first conductivity type, said device being a power MOSFET.

4. The power semiconductor device as defined by claim 3 wherein said first conductivity type is N type and said second conductivity type is P type.

5. The power semiconductor device as defined by claim 1 wherein said sixth and seventh doped regions are of first conductivity type.

6. The power semiconductor device as defined by claim 1 wherein said eighth doped region is of second conductivity type, said device being an IGBT.

7. The power semiconductor device as defined by claim 6 wherein said first conductivity type is N type and said second conductivity type is P type.

8. The power semiconductor device as defined by claim 7 wherein said sixth and seventh regions are of first conductivity type.

9. A power MOSFET device comprising

a semiconductor body having first and second major opposing surfaces with a first doped region of a first conductivity type therebetween,

first and second double diffused regions formed in said first doped region, said first and second double diffused regions being spaced apart and abutting said first surface,

first and second gate electrodes extending from said first surface into said first doped region, said first gate electrode being adjacent to said first double diffused region and spaced therefrom by an electrically insulative layer, said second gate electrode layer being adjacent to said second double diffused region and spaced therefrom by an electrically insulative layer,

said first region extending to said first surface between said first and second gate electrodes and separated therefrom by an electrically insulative layer of suitable thickness for voltage blocking, and

a drain region of said first conductivity type in said first doped region between said gate electrodes and abutting said first surface,

said first and second double diffused regions comprising source and channel regions of said device.

10. The power MOSFET device as defined by claim 9 wherein said drain region has a higher dopant concentration than said first region.

11. The power MOSFET device as defined by claim 10 and further including an ohmic contact to said source regions, an ohmic contact to said drain regions, and an ohmic contact to said gate electrodes.

12. The power MOSFET device as defined by claim 11 wherein said first conductivity type is N type and said second conductivity type is P type.

14. The IGBT device as defined by claim 10 and further including an ohmic contact to said anode, an ohmic contact to said cathode, and an ohmic contact to said gate.

15. The IGBT device as defined by claim 14 wherein said first conductivity type is N type and said second conductivity type is P type.

13. An insulated gate bipolar transistor (IGBT) device comprising

a semiconductor body having first and second major opposing surfaces with a first doped region of a first conductivity type therebetween,

first and second double diffused regions formed in said first doped region, said first and second double diffused regions being spaced apart and abutting said first surface,

first and second gate electrodes extending from said first region into said first doped region, said first gate electrode being adjacent to said first double diffused region and spaced therefrom by an electrically insulative layer, said second gate electrode being adjacent to said second double diffused region and spaced therefrom by an electrically insulative layer,

said first region extending towards said first surface between said first and second gate electrodes and separated from said first and second gate electrodes by an electrically insulative layer of suitable thickness for voltage blocking, and

a doped region of a second conductivity type in said first doped region between said first and second gate electrodes and functioning as an anode, said first and second double diffused regions functioning as cathodes and channel regions of said device.

16. A method of fabricating a power semiconductor device which is integrable in an integrated circuit comprising the steps of

a) providing a semiconductor body having first and second major opposing surfaces with a first doped region of a first conductivity type therebetween,

b) forming a first surface region in said first doped region with dopant of a second conductivity type, said surface region abutting said first surface,

c) forming a second surface region of said first conductivity type in said first surface region, said second surface region abutting said first surface,

d) forming a trench through said first surface region, said second surface region, and into said first doped region, said trench having exposed sidewalls and a bottom surface,

e) forming electrically insulative layers on said sidewalls,

f) forming conductive layers over said electrically insulative layers on said sidewalls,

g) forming electrically insulative layers of suitable thickness for voltage blocking on said conductive layers,

h) filling said trench with semiconductor material selectively epitaxially grown said bottom surface, and

i) doping a surface portion of said semiconductor material in said trench.

17. The method as defined by claim 16 wherein said conductive layers comprise doped polysilicon.

18. The method as defined by claim 17 and further including

forming contacts to said first and second surface regions,

forming contacts to said surface portion of said semiconductor material between said doped polysilicon layers, and

forming a contact to said doped polysilicon layers.

19. The method as defined by claim 16 wherein step i) includes doping a surface portion of said semiconductor material in said trench with dopant of said first conductivity type, said device being a MOSFET.

20. The method as defined by claim 16 wherein step i) includes doping a surface portion of said semiconductor material in said trench with dopant of said second conductivity type, said device being an IGBT.

21. The method as defined by claim 16 and further including after step b) the step of doping a portion of said first surface region with dopant of said second conductivity type to increase the dopant concentration.

22. The method as defined by claim 16 wherein step d) includes reactive ion etching.

23. The method as defined by claim 22 wherein steps e) and g) form thermally grown silicon oxide of variable thickness.

24. A microelectronic gated device comprising

a monocrystalline semiconductor substrate having a trench therein at one face thereof, said trench including a trench sidewall;

a relatively thin first insulating layer on said trench sidewall for gate oxide;

a gate electrode on said relatively thin first insulating layer;

a relatively thick second insulating layer on said gate electrode for voltage blocking;

a monocrystalline semiconductor region on said relatively thick second insulating layer, and extending from said substrate to said one face;

first contact means for electrically contacting said monocrystalline semiconductor region at said one face; and

second contact means for electrically contacting said monocrystalline semiconductor substrate at said one face.