Video signal generating apparatus

• US 5,349,388 A
• Filed: 03/17/1993
• Issued: 09/20/1994
• Est. Priority Date: 03/27/1992
• Status: Expired due to Term

• Current Assignee: Sony United Kingdom Limited (Sony Group Corp.)
• Original Assignee: Sony United Kingdom Limited (Sony Group Corp.)
• Inventors: Turner, Alan, Chouhan, Mukesh, Hedley, David J.
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): LEE, MICHAEL
• Application Number:
  US08/032,108
• Time in Patent Office: 552 Days
• Field of Search: 358/10, 358/139, 358/22, 358/160, 358/183, 358/182, 358/150, 324/76 R, 324/77 R, 328/187, 328/188, 364/579, 364/580
• US Class Current: 348/590
• CPC Class Codes: H04N 17/00 Diagnosis, testing or measuring for television systems or their details
• CPC Class Codes: H04N 5/262 Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects

Abstract

A video signal generating apparatus comprises a first microprocessor (10) including a memory (16) for receiving and storing in non-real time instructions for the generation of a range of video signals, such as test patterns, digital multi-effect keys or wipe patterns for a digital switcher, and a second microprocessor (14) for reading the instructions and generating a selected required video signal in real time.

Claims

1. A video signal generating apparatus comprising:

input means for inputting data relating to a video signal to be generated and representing signal pixel start addresses, signal start levels at said signal start addresses, and signal increment values;

a plurality of adder means for adding modification levels to said signal start levels for respective video outputs;

start value modification control means for generating a number of said modification levels, the number of said modification levels corresponding to the number of said adder means;

a plurality of accumulator means for accumulating the output signals of said adder means from said signal start addresses in dependence on said signal increment values, so as to generate demultiplexed video signals; and

combiner means for combining the demultiplexed signals so to generate said video signal.

2. Apparatus according to claim 1 wherein said input means inputs up/down data representing a polarity of the signal increment value.

3. Apparatus according to claim 1 wherein each said accumulator means and each said adder means operates at 1/n clock rate, where n is the number of said adder means.

4. Apparatus according to claim 1 further comprising:

signal start control means for generating an accumulation start trigger signal according to said signal start address and a count value; and

signal increment value generating means for generating signal increment values by multiplying the signal increment value by n (where n is the number of adder means), said accumulator means accumulating output signals of said adder means from said signal start address in dependence on said signal increment value and an accumulation start trigger signal so as to generate demultiplexed signals.

5. Apparatus according to claim 4 wherein each said accumulator means includes register means for memorizing data, inverting means for inverting a polarity of the output signal of the signal increment value generating means, first switch means for selectively outputting the output signal of said signal increment value generating means and the output signal of said inverting means in dependence on an up/down signal, adding means for adding the output signal of said first switch means to the output signal of said register means, and second switch means for selectively supplying the output signals of said adding means and the output signal of said adder means to said register means in dependence on said accumulation start trigger signal.

6. Apparatus according to claim 2 further comprising:

signal start control means for generating an accumulation start trigger signal according to said signal start address and a count value; and

signal increment value generating means for generating signal increment values by multiplying the signal increment data by n (where n is the number of adder means), said accumulator means accumulating output signals of said adder means from said signal start address in dependence on said signal increment value and an accumulation start trigger signal so as to generate demultiplexed signals.

7. Apparatus according to claim 6 wherein each said accumulator means includes register means for memorizing data, inverting means for inverting the polarity of the output signal of the signal increment value generating means, first switch means for selectively outputting the output signal of said signal increment value generating means and the output signal of said inverting means in dependence on an up/down signal, adding means fop adding the output signal of said first switch means to the output signal of said register means, and second switch means for selectively supplying the output signals of said adding means and the output signal of said adder means to said register means in dependence on said accumulation start trigger signal.