Multiple clock rate test apparatus for testing digital systems

• US 5,349,587 A
• Filed: 03/26/1992
• Issued: 09/20/1994
• Est. Priority Date: 03/26/1992
• Status: Expired due to Term

• Current Assignee: RPX Clearinghouse LLC (RPX Corporation)
• Original Assignee: Northern Telecom Limited (Nortel Networks Corporation)
• Inventors: Nadeau-Dostie, Benoit, Hassan, Abu S. M., Burek, Dwayne M., Sunter, Stephen K.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Palys, Joseph E.
• Application Number:
  US07/858,377
• Time in Patent Office: 908 Days
• Field of Search: 371/22.3, 371/22.4, 371/22.5, 371/22.6, 371/27
• US Class Current: 714/729
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/31858 Delay testing
• CPC Class Codes: G06F 11/24 Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests

Abstract

In methods and apparatus for testing a digital system, scannable memory elements of the digital system are configured in a scan mode in which the memory elements are connected to define a plurality of scan chains. A test stimulus pattern is clocked into each of the scan chains at a respective clock rate, at least two of the clock rates being different from one another. The memory elements of each scan chain are then configured in a normal operation mode in which the memory elements are interconnected by the combinational network for at least one clock cycle at a highest of the respective clock rates. The memory elements are then reconfigured in the scan mode, and a test response pattern is clocked out of each of the scan chains at its respective clock rate. The methods and apparatus are particularly useful for testing digital systems such as digital integrated circuits in which different memory elements are clocked at different rates during normal operation.

Claims

1. A method for testing a digital system comprising a plurality of scannable memory elements and at least one combinational network, the method comprising:

configuring the memory elements in a scan mode in which the memory elements are connected to define a plurality of scan chains;

clocking a test stimulus pattern into each of the scan chains at a respective clock rate, at least two of the clock rates being different from one another;

configuring the memory elements of each scan chain in a normal operation mode in which the memory elements are interconnected by the combinational network for at least one clock cycle at a highest of the respective clock rates;

configuring the memory elements in the scan mode; and

clocking a test response pattern out of each of the scan chains at its respective clock rate.

2. A method for testing a digital system comprising a plurality of scannable memory elements and at least one combinational network, the method comprising:

configuring the memory elements in a scan mode in which the memory elements are connected to define a plurality of scan chains;

clocking a test stimulus pattern into each of the scan chains at a respective clock rate during a respective scan-in interval, at least two of the clock rates being different from one another, all respective scan-in intervals overlapping in tome for a plurality of clock cycles at a highest of the respective clock rates;

configuring the memory elements of each scan chain in a normal operation mode during a respective normal mode interval, the memory elements of each scan chain being interconnected by the combinational network in the normal operation mode, all respective normal mode intervals overlapping in time for at least one clock cycle at the highest of the respective clock rates;

configuring the memory elements in the scan mode; and

clocking a test response pattern out of each of the scan chains at its respective clock rate during a respective scan-out interval, all respective scan-out intervals overlapping in time for a plurality of clock cycles at the highest of the respective clock rates.

3. A method as defined in claim 2, wherein the respective normal mode interval for each scan chain is a single clock cycle at the highest of the respective clock rates.

4. A method as defined in claim 3, comprising:

repeating the steps of configuring the memory elements in a scan mode, clocking a test stimulus pattern into each scan chain, configuring the memory elements in a normal operation mode for a clock cycle, configuring the memory elements in the scan mode, and clocking a test result pattern out of each scan chain for each test stimulus pattern in a series of successive test pattern sequences, each successive test pattern sequence being longer than preceding test pattern sequences;

comparing a test signature resulting from each test pattern sequence to an expected test signature; and

interrupting the series of test pattern sequences if a test signature resulting from a test pattern sequence does not correspond to the expected test signature for that test pattern sequence.

5. A method as defined in claim 2, wherein the respective normal mode interval for each scan chain is a single clock cycle at the respective clock rate of that scan chain.

6. A method as defined in claim 2, further comprising:

generating a test stimulus pattern in a random pattern generator operating at a highest of the respective clock rates of the scan chains; and

processing test response patterns in a test signature processor operating the highest of the respective clock rates of the scan chains.

7. A method as defined in claim 6, wherein:

each scan chain consists of memory elements which are clocked at a single clock rate during normal operation; and

the respective clock rate of each scan chain is substantially equal to the clock rate during normal operation of its memory elements.

8. A method as defined in claim 6, further comprising:

providing a first clock signal operating at the highest respective clock rate; and

deriving clock signals operating at the other respective clock rates from the first clock signal.

9. A method as defined in claim 8, comprising updating all memory elements during a common period of the first clock signal when the memory elements are configured in normal operation mode.

10. A method as defined in claim 9, wherein:

the first clock signal comprises pulses having a predetermined pulse width; and

the step of deriving clock signals comprises deriving clock signal operating at the other respective clock rates from the first clock signal, the derived clock signals comprising pulses having the predetermined pulse width.

11. A digital system comprising:

at least one combinational network;

a plurality of scannable memory elements, the memory elements being configurable in a normal operation mode in which the memory elements are interconnected by the combinational network and being configurable in a scan mode in which the memory elements are connected to define a plurality of scan chains;

a multiple clock generator for generating multiple clock signals for clocking test patterns into and out of each of the scan chains at a respective clock rate, at least tow of the clock rates being different from one another; and

a configuration controller for configuring the memory elements in scan mode to permit clocking of test stimulus patterns into each scan chain at its respective clock rate, for reconfiguring the memory elements in normal operation mode for at least one clock cycle at a highest of the respective clock rates, and for reconfiguring the memory elements in scan mode to permit clocking of test response patterns out of each scan chain at its respective clock rate.

12. A digital system as defined in claim 11, further comprising:

a test stimulus pattern generator operable at the highest of the respective clock rates of the scan chains to generate test stimulus patterns for clocking into the scan chains; and

a test response pattern processor operable at the highest of the respective clock rates of the scan chain to process test response patterns clocked out of the scan chains.

13. A digital system as defined in claim 12, implemented as an integrated circuit having at least one input terminal for connection of an input of the combinational network to an external network and at least one output terminal for connection of an output of the combinational network to an external network, the digital system further comprising:

a respective scannable memory element for each input terminal;

a respective input data selector operable to select between data applied to each input terminal and data stored in its respective scannable memory element for application to the corresponding input of the combinational network;

a respective scannable memory element for each output terminal; and

a respective output data selector operable to select between data applied to each output of the combinational network and data stored in the scannable memory element for application to the corresponding output terminal.

14. A digital system as defined in claim 13, wherein the respective scannable memory elements for each input terminal and each output terminal are connected to form at least one boundary scan chain when the scannable memory elements are configured in scan mode.

15. A digital system as defined in claim 14, wherein the boundary scan chain is provided with its own clock network so that the boundary scan chain can be clocked independently of other scan chains.

16. A digital system as defined in claim 13, further comprising a test access port, the test access port being coupled to at least one input terminal for receiving control signals from an external tester and at least one output terminal for sending test results to the external tester.

17. A digital system as defined in claim 12, wherein the multiple clock generator comprises means for deriving clock signals at the other respective clock rates from a clock signal operating at the highest respective clock rate.

18. A digital system as defined in claim 17, wherein the multiple clock generator comprises means for deriving two different clock signals at at least one of the respective clock rates for two phase clocking of memory elements in a scan chain operating at that respective clock rate.

19. A digital system as defined in claim 11, wherein:

a first memory element of a first scan chain clocked at a first clock rate supplies data via a combinational network to a second memory element of a second scan chain clocked at a second clock rate lower than the first clock rate when the memory elements are configured in normal operation mode; and

the scannable memory elements of the second scan chain are edge triggered flip-flops.