Data write control means

• US 5,349,669 A
• Filed: 02/02/1993
• Issued: 09/20/1994
• Est. Priority Date: 12/21/1988
• Status: Expired due to Term

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Sato, Hisatake, Arai, Yasuo
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): Sheikh, Ayaz R.
• Application Number:
  US08/012,618
• Time in Patent Office: 595 Days
• Field of Search: 395/750, 395/425, 395/325, 365/195, 365/226, 365/228, 365/229
• US Class Current: 365/228
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G06F 11/0754 by exceeding limits
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/1415 at system level
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

The present invention relates to a data protection (310) for preventing data from being erroneously written in a data holding circuit (307). A data protection circuit (311) receives a data protection set release select signal Sa provided by a processor (330), thereby causing a second timer (316) to start timing. The data protection circuit (311) further detects the level of a chip select signal CS provided by a power supply monitoring circuit (320) after the second timer (316) timed the time interval T2 and provides a data protection signal DP corresponding to the signal Sa to the data holding circuit (307) only in the case that the data protection circuit (311) judged that the main power supply (305) is at normal state.

Claims

1. A data write system for preventing a data store circuit from storing erroneous data therein so as to keep data stored therein while a data protect signal is generated, said data store circuit being supplied with a voltage by a power supply, comprising:

a power supply monitor coupled to the power supply for producing a first control signal selectively having first and second levels, the first level being produced when the voltage supplied from the power supply is greater than a predetermined level, the second level being produced when the voltage supplied from the power supply is less than or at the predetermined level;

a processor, connected to receive said voltage from the power supply, for generating a second control signal which has a data protect set mode and a data protect release mode and a third control signal which has a write permit mode and a write prohibit mode, in order to control said data store circuit;

a data protect setting and releasing circuit responsively coupled to said processor; and

a data protect circuit responsively coupled to said data protect setting and releasing circuit and selectively generating the data protect signal which has a protect mode and a release mode;

said data protect setting and releasing circuit, when the second control signal has the data protect set mode and the third control signal has the write permit mode, setting said data protect circuit to generate the data protect signal having a protect mode only when the first control signal has the first level a predetermined first period of time after the third control signal has the write permit mode, and when the second control signal has the data protect release mode and the third control signal has the write permit mode, said data protect setting and releasing circuit further setting said data protect circuit to generate the data protect signal only when the first control signal has the first level the predetermined first period of time after the third control signal has the write permit mode, otherwise said protect setting and release circuit causing said data protect circuit to continue outputting the data protect signal.

2. A data write system according to claim 1, further comprising:

a backup power supply for supplying a backup power supply voltage to said data store circuit; and

a switch circuit coupled to said power supply, said backup power supply, said data store circuit and said power supply monitor for connecting said power supply and said data store circuit when the first control signal has the first level, and connecting said backup power supply and said data store circuit when the first control signal has the second level.

3. A data write control system according to claim 1, wherein said data protect setting and releasing circuit does not detect the third control signal having the write permit mode during a second period of time from the first control signal being changed from the second level to the first level.

4. A data write control system comprising:

a power supply for supplying a power supply voltage;

a power supply monitor coupled to the power supply for producing a voltage level detecting signal having a first level when the power supply voltage is greater than a predetermined level and a second level when the power supply voltage is less than or at the predetermined level;

a processor coupled for receiving the power supply voltage, for generating a data protect setting and releasing signal having a protect set mode and a protect release mode, a protect writing signal having a write mode and a write prohibit mode and a write control signal;

a data protect circuit for generating a data protect signal having either a third level or a fourth level, the data protect circuit changing the level of the data protect signal corresponding to the mode of the data protect setting and releasing signal when the protect writing signal has the write mode and the voltage level detecting signal has the first level after a first period of time from detecting the write mode of the protect writing signal, otherwise said data protect circuit maintaining the level of the data protect signal;

a write control circuit coupled to said data protect circuit and said processor for generating a write enable signal in response to the write control signal when the data protect signal has the third level, said write control circuit generating a write prohibit signal when the data protect signal has the fourth level; and

a data store circuit coupled to the write control circuit for writing data when the write enable signal is received thereto.

5. A data write control system according to claim 4, further comprising:

a backup power supply for supplying a backup power supply voltage to said data store circuit; and

a switch circuit coupled to said power supply, said backup power supply, said data store circuit and said power supply monitor for connecting said power supply and said data store circuit when the voltage level detecting signal has the first level, and connecting said backup power supply and said data store circuit when the voltage level detecting signal has the second level.

6. A data write control system according to claim 4, wherein said data protect circuit does not detect the protect writing signal having the write mode during a second period of time from the voltage level detecting signal being changed from the second level to the first level.

7. A data write control system according to claim 6, wherein said data protect circuit has a first timer circuit for determining the second period of time.

8. A data write control system according to claim 6, wherein the first timer circuit has a rise time detecting circuit coupled to the power supply monitor for detecting that the voltage level detecting signal changes from the second level to the first level and a one shot pulse generator circuit for generating a one shot pulse signal in response to the detection of the level change.

9. A data write control system according to claim 4, wherein said data protect circuit has a second timer circuit for determining the first period of time.

10. A data write control system comprising:

a power supply for supplying a power supply voltage;

a power supply monitor coupled to the power supply for producing a voltage level detaching signal having a first level when the power supply voltage is greater than a predetermined level and a second level when the power supply voltage is less than or at the predetermined level;

a processor coupled for receiving the power supply voltage, for generating a data protect setting and releasing signal having a protect set mode and a protect release mode, a protect writing signal having a write mode and a write prohibit mode and a write control signal;

a data protect set and release discriminating circuit coupled to said processor and said power supply monitor for generating a discriminating signal having the protect mode when the data protect setting and releasing signal has a protect set mode and the protect writing signal has the write mode, said data protect set and release discriminating circuit generating the discriminating signal having a release mode when the data protect setting and releasing signal has the protect release mode and the protect writing signal has the write mode;

a data protect signal generating circuit coupled to said data protect set and release discriminating circuit for generating a data protect signal having either a third level or a fourth level, said data protect signal generating circuit generating the data protect signal having the third level where the voltage level detecting signal has the first level a predetermined time after the discriminating signal has the protect mode, said data protect signal generating circuit generating the data protect signal having the fourth level where the voltage level detecting signal has the first level the predetermined time after the discriminating signal has the release mode;

a write control circuit coupled to said data protect signal generating circuit and said processor for generating a write enable signal in response to the write control signal and the data protect signal having the third level, said write control circuit generating a write prohibit signal in response to the data protect signal having the fourth level; and

a data store circuit coupled to the write control circuit for storing data in response to the write enable signal.

11. A data write control system according to claim 10, further comprising:

a backup power supply for supplying a backup power supply voltage to said data store circuit; and

a switch circuit coupled to said power supply, said backup power supply, said data store circuit and said power supply monitor for connecting said power supply and said data store circuit when the voltage level detecting signal has the first level, and connecting said backup power supply and said data store circuit when the first control signal has the second level.

12. A data write control system according to claim 10, further comprising a first timer circuit coupled to said processor and said power supply monitor for prohibiting the transmission of the protect writing signal during a period of time from the voltage level detecting signal being changed from the second level to the first level.

13. A data write control system according to claim 10, wherein said first timer comprises:

a rising edge detecting circuit coupled to the power supply monitor for outputting a detect signal when the level of the voltage level detecting signal changes from the second level to the first level;

a first one shot pulse generating circuit coupled to said rising edge detecting circuit for outputting a first one shot pulse signal having a pulse width corresponding to the period of time in response to the detect signal; and

a first gate circuit coupled to said processor, said first one shot pulse generating circuit and said data protect set and release discriminating circuit, for prohibiting transmission of the protect writing signal from said processor to said data protect set and release discriminating circuit therethrough in response to the first one shot pulse signal.

14. A data write control system according to claim 13, wherein said data protect signal generating circuit comprises:

an oscillator for generating a clock signal;

a first counter circuit coupled to said data protect set and release discriminating circuit and said oscillator for generating a first count signal the predetermined time after the discriminating signal has the protect mode;

a second counter circuit coupled to said data protect set and release discriminating circuit and said oscillator for generating a second count signal the predetermined time after the discriminating signal has the release mode;

a second one shot pulse generating circuit coupled to the first counter for outputting a second one shot pulse signal in response to the first count signal;

a third one shot pulse generating circuit coupled to the second counter for outputting a third one shot pulse signal in response to the second count signal;

a second gate circuit coupled to said power supply monitor and said second one shot pulse generating circuit for transmitting the second one shot pulse signal therethrough in response to the voltage level detecting signal having the first level signal;

a third gate circuit coupled to said power supply monitor and said third one shot pulse generating circuit for transmitting the third one shot pulse signal therethrough in response to the voltage level detecting signal having the first level signal; and

a latch circuit coupled to said second and third gate circuits for outputting the data protect signal in response to the second and third one shot pulse signal.

16. A data write control system according to claim, 14, wherein said write control circuit comprises:

a fourth gate circuit coupled to said processor and said power supply monitor for transmitting the write control signal therethrough in response to the voltage level detecting signal having the first level, otherwise said fourth gate circuit outputting the write prohibit signal; and

a fifth gate circuit coupled to said fourth gate circuit and said data protect signal generating circuit for transmitting an output signal of said fourth gate circuit in response to the data protect signal having the third level, said fifth gate circuit generating the write prohibit signal in response to the data protect signal having the fourth level.

17. A data write control system according to claim 16, wherein said fourth gate circuit comprises:

an inverter having an input coupled to the processor and an output; and

a NAND gate having a first input coupled to the power supply monitor, and a second input coupled to the output of said inverter and output.

18. A data write control system according to claim 17, wherein said fifth gate circuit includes an OR gate having a first input coupled to the output of said NAND gate, a second input coupled to said data protect signal generating circuit and an output.

15. A data write control system according to claim 44, wherein said latch circuit is an RS flip-flop.