Integrated circuit programmable sequencing element apparatus

• US 5,349,670 A
• Filed: 11/08/1993
• Issued: 09/20/1994
• Est. Priority Date: 07/23/1986
• Status: Expired due to Fees

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Shankar, Kapil, Agrawal, Om P., Khu, Arthur H.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): MOHAMED, AYNI Y
• Application Number:
  US08/149,029
• Time in Patent Office: 316 Days
• Field of Search: 395/375, 395/775, 395/400, 364/716
• US Class Current: 712/245
• CPC Class Codes: G05B 19/045 using logic state machines, consisting only of a memory or a programmable logic device containing the logic for the controlled machine and in which the state of its outputs is dependent on the state of its inputs or part of its own output states, e.g. binary decision controllers, finite state controllers
• CPC Class Codes: G05B 2219/21115 Same connector can represent either input or output

Abstract

An integrated circuit programmable sequencing element apparatus on a single chip is provided which includes a PROM including first signal receiving circuitry and second signal providing circuitry; at least one feedback signal providing circuitry responsive to at least one second signal for providing at least one feedback signal; at least one input signal providing circuitry for providing at least one input signal; at least one control signal providing circuitry for providing at least one control signal; at least one programmable sequencing element circuitry for receiving said at least one control signal and the at least one input signal and for providing at least one programmable sequencing element signal; and selection circuitry for selecting at least between the at least one programmable sequencing element signal and the at least one feedback signal and for providing at least one selected signal to the first signal receiving circuitry.

Claims

1. A programmable integrated circuit comprising:

a PROM which receives a plurality of n respective PROM address signals and which provides a plurality of m PROM output signals, wherein the PROM stores an addressable set of at least 2ⁿ programmably-defined words each having at least m bits, and wherein m is greater than n and the set of m PROM output signals includes at least n first PROM output signals and at least one second PROM output signal;

external signal means for receiving from an external environment at least one external signal;

programmable sequencing element (PSE) means, operatively coupled to the external signal means and to the PROM, for providing at least n PSE output signals, said PSE means being responsive to the at least one external signal and to the at least one second PROM output signal such that the n PSE output signals constitute a programmably-defined function of one or both of the at least one external signal and the at least one second PROM output signal; and

selection means, coupled to the PROM to receive the at least n first PROM output signals and coupled to the PSE means to receive the at least n PSE output signals, for selecting n signals each from a respective one or the other of the received at least n first PROM output signals and the received at least n PSE output signals, and for providing the selected n signals to the PROM as the respective n-bit PROM address signals.

2. The integrated circuit of claim 1 wherein said at least one programmable sequencing element means includes a PROM.

3. The integrated circuit of claim 1 wherein said at least one programmable sequencing element means includes a programmable array logic device.

4. The integrated circuit of claim 1 wherein the external signal means further includes:

storage means for storing the at least one external signal and for supplying the stored external signal to the programmable sequencing element (PSE) means.

5. The integrated circuit of claim 1 wherein the external signal means further includes:

at least one first register, responsive to a supplied clock signal, for storing the at least one external signal in synchronism with the clock signal and for supplying the stored external signal to the programmable sequencing element (PSE) means.

6. The integrated circuit of claim 1 and further including:

output storage means for storing the at least n first PROM output signals and for supplying the stored n first PROM output signals to the selection means.

7. The integrated circuit of claim 1 and further including:

at least one output register, responsive to a supplied clock signal, for storing the at least n first PROM output signals in synchronism with the clock signal and for supplying the stored n first PROM output signals to the selection means.

8. The integrated circuit of claim 1 and further including:

first macrocell means for providing the at least n first PROM output signals to said selection means wherein the macrocell means includes programmable output means for outputting a programmably-selectable one or more of the at least n first PROM output signals out of said integrated circuit.

9. The integrated circuit of claim 1 and further including:

first storage means for storing the at least one external signal; and

first feedback means for providing the at least n first PROM output signals to said selection means.

10. The integrated circuit of claim 1 and further including:

first storage means for storing the at least one external signal;

first output storage means for storing the at least n first PROM output signals and for providing stored versions of the at least n first PROM output signals to the programmable sequencing element (PSE) means; and

programmable output selection means for programmably selecting among the at least n first PROM output signals and the stored versions of the at least n first PROM output signals as signals to be output from said integrated circuit.

11. The integrated circuit of claim 1 wherein:

said external signal means includes programmable direction control means, coupled to the external environment for programmably and alternatively outputting at least one of the at least n first PROM output signals to the external environment or receiving the at least one external signal from the external environment.

12. The integrated circuit of claim 1 and further including:

feedback means for providing to said PSE means the at least one second PROM output signal.

13. The integrated circuit of claim 1 and further including:

output storage means for storing the at least one second PROM output signal; and

feedback means for providing to said PSE means the stored at least one second PROM output signal.

14. The integrated circuit of claim 1 and further including:

first storage means for storing the at least one external signal;

first output storage means for storing the at least n first PROM output signals and for providing stored versions of the at least n first output signals to the programmable sequencing element (PSE) means; and

second output storage means for storing the at least one second PROM output signal and for providing a stored version of the at least one second PROM output signal to the programmable sequencing element (PSE) means.

15. The integrated circuit of claim 1 and further including:

storage means for storing the at least one external signal;

output storage means for storing the at least n first PROM output signals and for providing stored versions of the at least n first PROM output signals to the programmable sequencing element (PSE) means;

output selection means for selecting between the at least n first PROM output signals and the stored versions of the at least n first PROM output signal.

23. The integrated circuit of claim 2 wherein said programmable sequencing element means includes a PROM.

16. An integrated circuit comprising:

a PROM which receives respective n-bit PROM address signals and which provides a plurality of M PROM output signals including at least n first PROM output signals, M being greater than n;

external signal means for receiving from an external environment at least one external signal;

programmable sequencing element (PSE) means for providing at least n PSE output signals, said PSE means being responsive to at least one stored version of the at least n first PROM output signals;

selection means, coupled to the PROM and to the PSE means, for selecting the respective n-bit PROM address signals from among the at least n first PROM output signals and the at least n PSE signals;

output storage means for storing the at least n first PROM output signals and for providing stored versions of the at least n first PROM output signals to the programmable sequencing element (PSE) means;

output selection means for selecting between the at least n first PROM output signals and the stored versions of the at least n first PROM output signals; and

feedback means for providing the stored versions of the at least n first PROM output signals to said selection means;

wherein said external signal means, alternatively, provides to the external environment a programmably-selected one or more of the at least n first PROM output signals or provides to the external environment a programmably-selected one or more of the stored versions of the at least n first PROM output signals or receives from the external environment the at least n external signals.

17. The integrated circuit of claim 16 wherein:

said PSE means is responsive to at least one of the plurality of M PROM output signals other than said n first PROM output signals, to which said PSE means is said at least one other signal defining an at least one control signal; and

said integrated circuit further comprises output storage means for storing the at least one control signal.

18. The integrated circuit of claim 16 and further including:

feedback means for providing to said selection means the more than n first PROM output signals.

19. The integrated circuit of claim 16 and further including:

storage means for storing the at least one external signal;

output storage means for storing the more than n first PROM output signals and for providing stored versions of the more than n first PROM output signals; and

output selection means for selecting among the more than n first PROM output signals and the stored versions of the more than n first PROM output signals.

20. The integrated circuit of claim 16 wherein:

the at least one of the plurality of PROM output signals to which said PSE means is responsive includes at least one control signal; and

said integrated circuit further comprises output storage means for storing the at least one control signal.

21. The integrated circuit of claim 16 wherein said PROM provides at least 2 n first PROM output signals;

and wherein said external signal means receives at least n external signal.

22. An integrated circuit comprising:

a PROM which receives respective n-bit PROM address signals and which provides a plurality of M PROM output signals including at least n first PROM output signals and at least one control signal;

external signal means for alternatively receiving from an external environment at least one external signal or providing to the external environment the at least n first PROM output signals;

programmable sequencing element (PSE) means for providing at least n PSE output signals, said PSE means being responsive to the at least one control signal;

storage means for storing the at least one external signal;

first output storage means for storing the at least n first PROM output signals;

second output storage means for storing the at least one control signal; and

selection means, coupled to the PROM and to the PSE means, for selecting the respective n-bit PROM address signals from among the at least n first PROM output signals and the at least n PSE signals.

24. The integrated circuit of claim 22 wherein said programmable sequencing element means includes a programmable array logic device.

25. An integrated circuit comprising:

a PROM which receives respective n-bit PROM address signals and which provides a plurality of M PROM output signals;

external signal means for receiving respective at least n-bit external signals from an external environment;

storage means for storing the respective at least n-bit external signals and for providing stored versions of the respective at least n-bit external signals;

address counter means for incrementing respective n-bit counter signals to produce respective n-bit incremented counter signals; and

selection means, coupled to the PROM and to the storage means and to the address counter means, for selecting the respective n-bit PROM address signals from among the respective incremented counter signals, the respective at least n-bit external signals, and the stored versions of the at least n-bit external signals;

wherein said counter means receives a respective n-bit PROM address signal selected by said selection means and produces respective incremented versions of the selected respective n-bit PROM address signal as the respective incremented counter signals.

26. The integrated circuit of claim 25 wherein the plurality of M PROM output signals include at least one control signal and said selection means responsive to the at least one control signal.

27. The integrated circuit of claim 25 wherein the plurality of M PROM output signals include at least one control signal and said counter means is responsive to the at least one control signal.

28. The integrated circuit of claim 25 wherein the plurality of PROM output signals include multiple control signals;

and said selection means and said counter means are respectively responsive to respective control signals.