Data acquisition systems with programmable bit-serial digital signal processors

• US 5,349,676 A
• Filed: 02/11/1991
• Issued: 09/20/1994
• Est. Priority Date: 02/11/1991
• Status: Expired due to Term

• Current Assignee: General Electric Company, Yokogawa Electric Corporation
• Original Assignee: General Electric Company
• Inventors: Fujino, Kenji, Garverick, Steven L.
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): SHAH, ALPESH
• Application Number:
  US07/653,935
• Time in Patent Office: 1,317 Days
• Field of Search: 395/800, 395/425, 395/775, 395/100, 364/736-784, 324/76 R
• US Class Current: 712/36
• CPC Class Codes: G01R 21/006 Measuring power factor
• CPC Class Codes: G05B 19/0423 Input/output
• CPC Class Codes: G05B 2219/25254 DSP digital signal processor
• CPC Class Codes: G06F 15/7842 on one IC chip (single chip microcontrollers)
• CPC Class Codes: G06F 2207/4814 Non-logic devices, e.g. operational amplifiers
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 7/5446 using crossaddition algorithms, e.g. CORDIC

Abstract

A monolithic integrated circuit as may be used in combination with a plurality of sensors for generating respective sensor output signals, which monolithic integrated circuit includes means for converting each sensor output signal to bit-serial digital format, together with some initial processing circuitry comprising a bit-serial multiply-add processor. This processor includes a bit-serial digital multiplier for multiplying a first digital processor input signal in bit-serial form by a second digital processor input signal to generate a digital product signal, a digital adder for adding a third digital processor input signal to the digital product signal to generate a digital sum signal, and means for supplying a digital processor output signal with bits correspond-ing to those of said digital sum signal. A memory system provides memory for storing program instructions, memory for storing successive values of the second digital processor input signal, memory for storing successive values of the third digital processor input signal, and memory for storing successive values of the digital processor output signal as written into the memory system. The first digital processor input signal can be selected from among the sensor output signals as converted to bit-serial digital format. The second digital processor input signals applied to the bit-serial multiply-add processor are at least at selected times read from the memory system, as are the third digital processor input signals applied to the bit-serial multiply-add processor. A controller retrieves stored program instructions in a prescribed order from the memory for storing program instructions and generates control signals for controlling at least the reading and writing of the memory system, as well as the selecting of the first digital processor input signal.

Claims

1. A monolithic integrated circuit having disposed therewithin:

a bit-serial multiply-add processor, including

a bit-serial digital multiplier for multiplying a first bit-serial processor input signal by a second bit-serial processor input signal to generate a bit-serial product signal,

a bit-serial digital adder for adding a third bit-serial processor input signal to said bit-serial product signal to generate a bit-serial sum signal, and

means for supplying a bit-serial processor output signal with bits corresponding to those of said bit-serial sum signal;

a first multiplexer for supplying said first bit-serial processor input signal responsive to a selected one of a plurality of bit-serial input signals, including said bit-serial sum signal, supplied to said first multiplexer;

a second multiplexer for supplying said second bit-serial processor input signal responsive to a selected one of a plurality of bit-serial input signals, including said bit-serial sum signal, supplied to said second multiplexer;

a third multiplexer for supplying said third bit-serial processor input signal responsive to a selected one of a plurality of bit-serial input signals, including said bit-serial sum signal, supplied to said third multiplexer;

an on-chip memory;

means for reading during each of first selected times stored information from a location within said on-chip memory selected during each of said first selected times to said first, second and third multiplexers as respective bit-serial input signals thereto;

means for reading during each of second selected times stored information from a location within said on-chip memory selected during each of said second selected times to said first, second and third multiplexers as respective input signals thereto; and

means for writing during each of third selected times said bit-serial processor output signal to a location within said on-chip memory selected during each said third selected times.

2. A monolithic integrated circuit as set forth in claim 1 having disposed therewithin:

analog-to-digital converter means for converting a plurality of analog input signals, as supplied to said integrated circuit, to a respective number of bit-serial analog-to-digital conversion results; and

means for applying at least selected ones of said analog-to-digital conversion results, on a time-division multiplex basis, to said first multiplexer as one of its said plurality of respective bit-serial input signals.

3. A combination including a monolithic integrated circuit as set forth in claim 1 together with:

a read-only memory for storing program instructions and for storing successive coefficient values, said monolithic integrated circuit as set forth in claim 10 further including;

controller means for retrieving stored program instructions in a prescribed order from said read-only memory and for generating control signals for controlling the reading and writing of said on-chip memory, the selecting of said first bit-serial processor input signal by said first multiplexer, the selecting of said second bit-serial processor input signal by said second multiplexer and the selecting of said third bit-serial processor input signal by said third multiplexer.

4. A monolithic integrated circuit as set forth in claim 1 wherein said on-chip memory is of a type into which parallel-bit memory input signal is written and from which parallel-bit memory output signal is read;

wherein said means for supplying a digital processor output signal includes a serial-in/parallel-out register receptive of said bit-serial sum signal;

wherein said means for reading during each of first selected times stored information from said first location in said on-chip memory includes a first parallel-in/serial-out register for converting said parallel-bit memory output signal to bit-serial input signal for application to said first, second and third multiplexers as respective bit-serial input signals thereto; and

wherein said means for reading during each of second selected times stored information from said first location in said on-chip memory includes a second parallel-in/serial-out register for converting said parallel-bit memory output signal to bit-serial input signal for application to said first, second and third multiplexers as respective bit-serial input signals thereto.

5. In combination with a plurality of sensors for generating respective sensor output signals, a monolithic integrated circuit having disposed therewithin:

a bit-serial multiply-add processor, including

a bit-serial digital multiplier for multiplying a first bit-serial processor input signal by a second bit-serial processor input signal to generate a bit-serial product signal,

a bit-serial digital adder for adding a third bit-serial processor input signal to said bit-serial product signal to generate a bit-serial sum signal, and

means for supplying a bit-serial processor output signal with bits corresponding to those of said bit-serial sum signal;

a first multiplexer for supplying said first bit-serial processor input signal responsive to a selected one of a plurality of bit-serial input signals, including said bit-serial sum signal, supplied to said first multiplexer;

a second multiplexer for supplying said second bit-serial processor input signal responsive to a selected one of a plurality of bit-serial input signals, including said bit-serial sum signals, supplied to said second multiplexer;

a third multiplexer for supplying said third bit-serial processor input signal responsive to a selected one of a plurality of bit-serial input signals, including said bit-serial sum signal, supplied to said third multiplexer;

an on-chip memory;

means for reading during each of first selected times stored information from a location within said on-chip memory selected during each of said first selected times to said first, second and third multiplexers as respective bit-serial input signals thereto;

means for reading during each of second selected times stored information from a location within said on-chip memory selected during each of said second selected times to said first, second and third multiplexers as respective input signals thereto; and

means for writing during each of third selected times said bit-serial processor output signal to a location within said on-chip memory selected during each of said third selected times;

analog-to-digital converter means for converting said sensor output signals, as supplied to said integrated circuit, to a respective number of bit-serial analog-to-digital conversion results; and

means for applying at least selected ones of said analog-to-digital conversion results, on a time-division multiplex basis, to said first multiplexer as one of its said plurality of respective bit-serial input signals.

6. A combination as set forth in claim 5 wherein said sensors are arranged for sensing respective electrical parameters associated with a set of electric power lines.

7. A combination as set forth in claim 6 wherein said set of electric power lines has a plurality of phases.

8. A combination as set forth in claim 6 wherein said monolithic integrated circuit includes therewithin:

a bank of registers for temporarily storing at least two successive bit-serial sum signals from said multiply-add processor;

a further digital processor for processing temporarily stored signals read from said bank of registers to generate digital output signals by a successive approximation procedure.

9. A monolithic integrated circuit as set forth in claim 8 in combination with:

a digital meter for displaying a value of said digital output signals.

10. A combination as set forth in claim 8 wherein said sensors are arranged for sensing current in each phase of said set of electric power lines.

11. A combination as set forth in claim 10 including:

a read-only memory, for storing program instructions to instruct said multiply-add processor to correct errors in phase current samples and to instruct said multiply-add processor and further digital processor in calculating r-m-s phase current values, and for storing coefficient values including those indicative of errors arising in said sensors or said analog-to-digital converter means; and

controller means, included within said monolithic integrated circuit, for retrieving stored program instructions in a prescribed order from said read-only memory and for generating control signals for controlling the reading and writing of said on-chip memory, the selecting of said first bit-serial processor input signal by said first multiplexer, the selecting of said second bit-serial processor input signal by said second multiplexer and the selecting of said third bit-serial processor input signal by said third multiplexer.

12. A monolithic integrated circuit as set forth in claim 11 including therewithin:

a pulse duration modulator for generating regularly recurring electric pulses having durations determined in response to said digital output signals.

13. A combination as set forth in claim 11 including therewithin:

a pulse duration modulator for generating regularly recurring electric pulses having durations determined in response to said digital output signals; and

a meter with D'"'"'Arsonval movement for measuring average intensity of said electric pulses.

14. A combination as set forth in claim 8 wherein said sensors are arranged for sensing voltage across each said phase of said set of electric power lines.

15. A combination as set forth in claim 14 including:

a read-only memory for storing program instructions to instruct said multiply-add processor to correct errors in phase voltage samples and to instruct said multiply-add processor and further digital processor in calculating r-m-s phase voltage values and for storing coefficient values including those indicative of errors arising in said sensors or said analog-to-digital converter means; and

controller means, included within said monolithic integrated circuit, for retrieving stored program instructions in a prescribed order from said read-only memory and for generating control signals for controlling the reading and writing of said on-chip memory, the selecting of said first bit-serial processor input signal by said first multiplexer, the selecting of said second bit-serial processor input signal by said second multiplexer and the selecting of said third bit-serial processor input signal by said third multiplexer.

16. A combination as set forth in claim 15 including therewithin:

a pulse duration modulator for generating regularly recurring electric pulses having durations determined in response to said digital output signals; and

a meter with D'"'"'Arsonval movement for measuring average intensity of said electric pulses.

17. A combination as set forth in claim 8 wherein said sensors are arranged for sensing current in at least a first phase of said set of electric power lines and for sensing voltage across at least said first phase of said set of electric power lines.

18. A combination as set forth in claim 17 including:

a read-only memory, for storing program instructions for instructing said multiply-add processor to correct errors in current and voltage samples for each phase and to instruct said multiply-add processor and further digital processor in calculating power for at least said first phase, and for storing coefficient values including those indicative of errors arising in said sensors or said analog-to-digital converter means; and

controller means, included within said monolithic integrated circuit, for retrieving stored program instructions in a prescribed order from said read-only memory and for generating control signals for controlling the reading and writing of said on-chip memory, the selecting of said first bit-serial processor input signal by said first multiplexer, the selecting of said second bit-serial processor input signal by said second multiplexer and the selecting of said third bit-serial processor input signal by said third multiplexer.

19. A combination as set forth in claim 18 wherein said set of electric power lines has plural phases;

wherein there is included means for sensing the current and voltage of each of said plural phases; and

wherein said read-only memory stores program instructions for instructing said multiply-add processor and further digital processor in the calculation of total power for all of said plural phases of said set of electric power lines.

20. A combination as set forth in claim 19 including therewithin:

apparatus for providing a digital-readout of the total power for all of said plural phases of said set of electric power lines to a human observer.

21. A combination as set forth in claim 17 including:

a read-only memory, for storing program instructions for instructing said multiply-add processor to correct errors in current and voltage samples for each phase and to instruct said multiply-add processor and further digital processor in calculating reactive power or vars for each phase, and for storing coefficient values including those indicative of errors arising in said sensors or said analog-to-digital converter means; and

controller means, included within said monolithic integrated circuit, for retrieving stored program instructions in a prescribed order from said read-only memory and for generating control signals for controlling the reading and writing of said on-chip memory, the selecting of said first bit-serial processor input signal by said first multiplexer, the selecting of said second bit-serial processor input signal by said second multiplexer and the selecting of said third bit-serial processor input signal by said third multiplexer.

22. A combination as set forth in claim 21 wherein said set of electric power lines has plural phases;

wherein there is included means for sensing the current and voltage of each of said plural phases; and

wherein said read-only memory stores program instructions for instructing said multiply-add processor and further digital processor in the calculation of total reactive power or vars for all of said plural phases of said set of electric power lines.

23. A combination as set forth in claim 22 including therewithin:

apparatus for providing a digital-readout of the total reactive power or vats for all of said plural phases of said set of electric power lines to a human observer.

24. A combination as set forth in claim 17 including:

a read-only memory, for storing program instructions for instructing said multiply-add processor to linearize current and voltage samples for each phase, for storing program instructions for instructing said multiply-add processor and further digital processor to calculate r-m-s current and voltage for each phase, for storing program instructions for instructing said further digital processor to calculate the power factor for each phase, and for storing coefficient values including those indicative of errors arising in said sensors or said analog-to-digital converter means; and

controller means, included within said monolithic integrated circuit, for retrieving stored program instructions in a prescribed order from said read-only memory and for generating control signals for controlling the reading and writing of said on-chip memory, the selecting of said first bit-serial processor input signal by said first multiplexer, the selecting of said second bit-serial processor input signal by said second multiplexer and the selecting of said third bit-serial processor input signal by said third multiplexer.

25. A combination as set forth in claim 24 including therewithin:

apparatus for providing a digital-readout of the power factor to a human observer.