×

Multipurpose bus interface utilizing a digital signal processor

  • US 5,349,685 A
  • Filed: 05/05/1992
  • Issued: 09/20/1994
  • Est. Priority Date: 05/05/1992
  • Status: Expired due to Fees
First Claim
Patent Images

1. A multipurpose bus interface circuit for interfacing a first communications bus to a second communications bus, said second communications bus being a Manchester encoded time division multiplexed serial data bus having first, second, third and fourth primary avionics buses and an electronic warfare bus, said multipurpose bus interface circuit comprising:

  • an integrated circuit memory card;

    first transceiver means for receiving data from and transmitting data to said first communications bus, said first transceiver means formatting the data received thereby to a digital format;

    programmable array logic means for receiving a plurality of read/write control signals, and for decoding said read/write control signals so as to control the transfer of said digital data between said first communications bus and said integrated circuit memory card;

    digital signal processor means for providing said plurality of read/write control signals and a plurality of eight bit control words, said digital signal processor means having direct access to said integrated circuit memory card such that data to or from said first communications bus is transferred between said integrated circuit memory card and said first communications bus via said first transceiver means and said digital signal processor means and data to or from said second communications bus is transferred between said integrated circuit memory card and said second communications bus via said digital signal processor means;

    an electrically erasable programmable read only memory electrically coupled to said digital signal processor means, said electrically erasable programmable read only memory containing software for said digital signal processor means, said software controlling the handling of data to and from said first communications bus and said software controlling the handling of data to and from said second communications bus by enabling the operation of said digital signal processor means according to bus standards and data protocols and formats of Military Standard 1553;

    means for encoding digital data from said integrated circuit memory card so as to provide Manchester encoded data and for decoding Manchester encoded data so as to provide digital data, said encoding and decoding means providing an interface between said digital signal processor means and said second communications bus;

    second transceiver means for transmitting the Manchester encoded data provided by said encoder and decoder means to said second communications bus and for receiving from said second communications bus Manchester encoded data for decoding by said encoder and decoder means;

    transformer means for electrically isolating said second communications bus from said digital signal processing means;

    programmable peripheral interface means for receiving said eight bit control words from said digital signal processor means and decoding said eight bit control words to provide a first avionics bus enable signal, a second avionics bus enable signal, a third avionics bus enable signal, a fourth avionics bus enable signal and an electronic warfare bus enable signal;

    a first driver circuit electrically coupled to said programmable peripheral interface means to receive said first, second, third and fourth avionics bus enable signals;

    a first relay electrically coupled to said transformer means, said first driver circuit and said first primary avionics bus;

    a second relay electrically coupled to said transformer means, said first driver circuit and said second primary avionics bus;

    a third relay electrically coupled to said transformer means, said first driver circuit and said third primary avionics bus;

    a fourth relay electrically coupled to said transformer means, said first driver circuit and said fourth primary avionics bus;

    said first driver circuit responsive to said first, second, third and fourth avionics bus enable signals selectively enabling one of said first, second, third and fourth relays to allow for a first transfer of said Manchester encoded data between said encoder and decoder means and one of said first, second, third and fourth primary avionics buses through the one of said first, second, third and fourth relays selectively enabled by said first driver circuit;

    a second driver circuit electrically coupled to said programmable peripheral interface means for receiving said electronic warfare bus enable signal; and

    a fifth relay electrically coupled to said transformer means, said second driver circuit and said electronic warfare bus;

    said second driver circuit responsive to said electronic warfare bus enable signal enabling said fifth relay to allow for a second transfer of said Manchester encoded data between said encoding and decoding means and said electronic warfare bus.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×