Pacemaker telemetry system
First Claim
1. A telemetry system for communicating digital information via a radio-frequency signal, comprising:
- an antenna, adapted to receive said radio-frequency signal;
an RF detect circuit, coupled to said antenna and responsive to said radiofrequency signal to convert said radio-frequency signal into a digital pulse stream;
a clock, responsive to assertion of a clock activation signal to produce a clock signal at a clock output terminal thereof;
a clock activation circuit, coupled to said RF detect circuit to receive said digital pulse stream, and coupled to said clock, said clock activation circuit responsive to a first predetermined characteristic of said digital pulse stream to assert said clock activation signal, and responsive to a second predetermined characteristic of said digital pulse stream to deassert said clock activation signal;
a counter, coupled to said clock output terminal and adapted to present a plurality of count value output signals representing said counter'"'"'s count value at a plurality of output terminals thereof, said counter responsive to a cycle of said clock signal to increment said count value;
a logic array, coupled to said counter output terminals to receive said count value output signals, and coupled to said RF detect circuit to receive said digital pulse stream, said logic array responsive to a first predetermined combination of said counter value output signals and said digital pulse stream to assert a first output signal indicative of a digital "1" encoded into said radio-frequency signal, said logic array responsive to a second predetermined combination of said counter value output signals and said digital pulse stream to assert a second output signal indicative of a digital "0" encoded into said radio-frequency signal.
1 Assignment
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Accused Products
Abstract
An implantable medical device telemetry system provides a means for decoding telemetry downlink information transmitted from an external unit to an implanted medical device, and for encoding telemetry uplink signals to be transmitted from the implanted device to the external unit. A novel system architecture results in a very small telemetry subsystem in the implanted device and a very flexible system adaptable to be used in conjunction with various telemetry formats of various implanted devices. A programmable logic array (PLA) structure that is mask programmable and which may further be partially RAM programmable serves as the basis of the telemetry subsystem. For downlink telemetry, a counter is enabled during intervals of interest in the downlink RF burst stream. The counter value at the end of such an interval is then applied to the variable inputs of the PLA tier decoding in accordance with a selected telemetry protocol. For uplink telemetry, the counter and PLA is used to control transmission of uplink telemetry pulses, such that pulses are pulse-position modulated in accordance with data to be transmitted. Various different telemetry protocols may be supported by the same telemetry circuit, which may be mask-programmed at the time of manufacture to be compatible with one or more different telemetry protocols.
400 Citations
27 Claims
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1. A telemetry system for communicating digital information via a radio-frequency signal, comprising:
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an antenna, adapted to receive said radio-frequency signal; an RF detect circuit, coupled to said antenna and responsive to said radio frequency signal to convert said radio-frequency signal into a digital pulse stream; a clock, responsive to assertion of a clock activation signal to produce a clock signal at a clock output terminal thereof; a clock activation circuit, coupled to said RF detect circuit to receive said digital pulse stream, and coupled to said clock, said clock activation circuit responsive to a first predetermined characteristic of said digital pulse stream to assert said clock activation signal, and responsive to a second predetermined characteristic of said digital pulse stream to deassert said clock activation signal; a counter, coupled to said clock output terminal and adapted to present a plurality of count value output signals representing said counter'"'"'s count value at a plurality of output terminals thereof, said counter responsive to a cycle of said clock signal to increment said count value; a logic array, coupled to said counter output terminals to receive said count value output signals, and coupled to said RF detect circuit to receive said digital pulse stream, said logic array responsive to a first predetermined combination of said counter value output signals and said digital pulse stream to assert a first output signal indicative of a digital "1" encoded into said radio-frequency signal, said logic array responsive to a second predetermined combination of said counter value output signals and said digital pulse stream to assert a second output signal indicative of a digital "0" encoded into said radio-frequency signal. - View Dependent Claims (2, 3, 4, 5)
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6. A telemetry system for receiving and decoding digital data encoded in a radio-frequency signal, comprising:
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a telemetry coil, adapted to receive said radio-frequency signal; a detector circuit, coupled to said coil and responsive to a first predetermined characteristic in said received radio-frequency signal to assert a wakeup signal and thereafter responsive to a second predetermined characteristic in said received radio-frequency signal to assert a detect signal; a clock, coupled to said detector circuit and responsive to assertion of said detect signal to produce a clock signal; a counter, coupled to said clock to receive said clock signal, and coupled to said detector circuit to receive said detect signal, said counter having a plurality of output terminals for presenting a count value thereon, said counter responsive to said clock signal to said detect signal to reset said count value and to count clock cycles of said clock signal; a programmed logic array, having a first plurality of input terminals coupled to said counter output terminals to receive said count value, said logic array further having a plurality of output terminals, said logic array responsive to a first predetermined count value to assert a signal on a first one of said plurality of output terminals and responsive to a second predetermined count value to assert a signal on a second one of said plurality of output terminals; a first decoding circuit, coupled to said detector circuit and to said logic array, said first decoding circuit responsive to said received signal and to assertion of said signal on said first logic array output terminal to assert a first decoder output signal; a second decoding circuit, coupled to said detector circuit and to said logic array, said second decoding circuit responsive to said received signal and to assertion of said signal on said second logic array output terminal to assert a second decoder output signal; a digital data storage circuit, coupled to said first and second decoding circuits and responsive to assertion of said first decoder output signal to store a binary "0" bit and responsive to assertion of said second decoder output signal to store a binary "1" bit. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A telemetry system for transmitting digital data encoded in a radio-frequency signal, comprising:
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a telemetry coil, responsive to a telemetry driver signal to transmit a radio frequency burst; a telemetry driver circuit, having an output terminal coupled to said coil and having an input terminal, said telemetry driver circuit responsive to assertion of a signal at said input terminal to apply said telemetry driver signal to said coil; a digital memory circuit, adapted to store said digital data; a clock, having an enable input terminal and a clock output terminal, said clock responsive to assertion of an uplink enable signal applied to said enable input terminal to produce a clock signal at said clock output terminal; a counter having a plurality of output terminals and further having a clock input terminal coupled to said clock output terminal, said counter responsive to said clock signal on said clock output terminal to count clock cycles therein, said counter adapted to present a clock cycle count value on said output terminals; a state register comprising a plurality of bit storage locations, said state register having a plurality of state input terminals, a clock input terminal coupled to said clock output terminal, and a plurality of state output terminals, said state register responsive to a cycle of said clock signal to store, in said plurality of bit storage locations, data corresponding to signals applied to said state input terminals; a RAM-programmable logic array having a first plurality of input terminals coupled to said counter output terminals, a second plurality of input terminals coupled to said state register state output terminals, and at least one output terminal coupled to said telemetry driver circuit input terminal, said logic array coupled to said digital memory circuit and responsive to said data stored in said digital memory circuit to program an output term such that said logic array is responsive to a match between said count value applied to said first plurality of input terminals and signals on said state output terminals, on the one hand, and said digital data, on the other hand, to assert a signal at said output terminal. - View Dependent Claims (13)
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14. A telemetry system for transmitting an uplink radio-frequency signal having uplink digital data encoded therein and for receiving and decoding downlink digital data encoded in a downlink radio-frequency signal, said telemetry system comprising:
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a telemetry coil, adapted to receive said downlink radio-frequency signal; a detector circuit, coupled to said coil and responsive to a first predetermined characteristic in said downlink radio-frequency signal to assert a wakeup signal and responsive to assertion of said wake-up signal and a second predetermined characteristic in said downlink radio-frequency signal to assert a detect signal; a clock, having an enable input coupled to said detector circuit to receive said detect signal, said clock responsive to assertion of said detect signal at said enable input to produce a clock signal; a counter, coupled to said clock to receive said clock signal, said counter responsive to said clock signal to count clock cycles therein, said counter having a plurality of output terminals for presenting a count value thereon; a programmed logic array, having a first plurality of input terminals coupled to said counter output terminals to receive said count value, said logic array further having a plurality of output terminals, said logic array responsive to a first predetermined count value to assert a signal on a first one of said plurality of output terminals and responsive to a second predetermined count value to assert a signal on a second one of said plurality of output terminals; a first decoding circuit, coupled to said detector circuit and to said logic array, said first decoding circuit responsive to said downlink signal and to assertion of said signal on said first logic array output terminal to assert a first decoder output signal; a second decoding circuit, coupled to said detector circuit and to said logic array, said second decoding circuit responsive to said downlink signal and to assertion of said signal on said second logic array output terminal to assert a second decoder output signal; a digital data storage circuit, coupled to said first and second decoding circuits and responsive to assertion of said first decoder output signal to store a binary "0" bit and responsive to assertion of said second decoder output signal to store a binary "1" bit; a telemetry driver circuit, having an output terminal coupled to said coil and having an input terminal, said telemetry driver circuit responsive to assertion of a signal at said input terminal to apply said telemetry driver signal to said coil; an uplink control circuit, having an uplink data output terminal and an uplink enable output terminal, said uplink output terminal coupled to said clock enable signal such that said clock is responsive to assertion of a signal on said uplink enable output terminal to present said clock signal on said clock output terminal; a digital memory circuit, adapted to store said uplink data presented on said uplink data output terminal; a state register comprising a plurality of bit storage locations, said state register having a plurality of state input terminals, a clock input terminal coupled to said clock output terminal, and a plurality of state output terminals, said state register responsive to a cycle of said clock signal to store, in said plurality of bit storage locations, data corresponding to signals applied to said state input terminals; said logic array having further having a second plurality of input terminals coupled to said state register state output terminals, and at least one output terminal coupled to said telemetry driver circuit input terminal, said logic array coupled to said digital memory circuit and responsive to said data stored in said digital memory circuit to program an output term such that said logic array is responsive to a match between said count value applied to said first plurality of input terminals and signals on said state output terminals, on the one hand, and said digital data, on the other hand, to assert a signal at said output terminal. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A telemetry system for transmitting an uplink radio-frequency signal having uplink digital data encoded therein and for receiving and decoding downlink digital data encoded in a downlink radio-frequency signal, said telemetry system comprising:
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a telemetry coil, adapted to receive said downlink radio-frequency signal; a detector circuit, coupled to said coil and responsive to a first predetermined characteristic in said downlink radio-frequency signal to assert a wake up signal and responsive to a second predetermined characteristic in said downlink radio-frequency signal to assert a detect signal; a clock, having a clock output terminal, said clock adapted to produce a clock signal at said clock output terminal; a counter, coupled to said clock output terminal to receive said clock signal, said counter responsive to said clock signal to count clock cycles therein, said counter having a plurality of output terminals for presenting a count value thereon; a logic array, having; a first plurality of input terminals coupled to said counter output terminals to receive said count value; a detect input coupled to said detector circuit to receive said detect signal; a match input; a downlink data output terminal for presenting a downlink data output signal thereon; and a store output terminal for presenting a store output signal;
said logic array responsive to a first predetermined count value presented on said counter output terminals concurrently with assertion of said detect signal to deassert said downlink data output signal and to assert said store output signal, and responsive to a second predetermined count value presented on said counter output terminals concurrently with assertion of said detect signal to assert said downlink data output signal and said store output signal;a digital data storage circuit, coupled to said downlink data output terminal and to said store output terminal, said storage circuit responsive to assertion of said store signal to store a binary "0" bit when said downlink data signal is deasserted and to store a binary "1" bit when said downlink data signal is asserted; a telemetry driver circuit, having an output terminal coupled to said coil and having an input terminal, said telemetry driver circuit responsive to assertion of a signal at said input terminal to apply said telemetry driver signal to said coil; a state register comprising a plurality of bit storage locations, said state register having a plurality of state input terminals, a clock input terminal coupled to said clock output terminal, and a plurality of state output terminals, said state register responsive to a cycle of said clock signal to store, in said plurality of bit storage locations, state data corresponding to signals applied to said state input terminals; a comparator circuit, having input terminals coupled to said counter output terminals and to said data storage circuit, and having a match output terminal coupled to said logic array match input, said comparator circuit responsive to a match between said count value and data stored in said storage circuit to assert a signal on said match output terminal; said logic array having further having a second plurality of input terminals coupled to said state register state output terminals, and a telemetry out output terminal coupled to said telemetry driver circuit input terminal, said logic array responsive to assertion of said match signal and a predetermined combination of said state data to assert a signal at said telemetry out output terminal.
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22. A telemetry system for receiving and decoding downlink digital data encoded in a downlink telemetry signal, and for encoding and transmitting uplink digital data in an uplink telemetry signal, said telemetry system comprising:
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a telemetry coil, adapted to receive said downlink telemetry signal, and to transmit said uplink telemetry signal in accordance with a telemetry driver signal; a telemetry driver circuit having an input terminal and an output terminal coupled to said telemetry coil, said driver circuit responsive to a telemetry out signal applied to said telemetry driver input terminal to present said telemetry driver signal on said telemetry driver output terminal; a detector circuit coupled to said telemetry coil to receive said downlink telemetry signal therefrom, said detector circuit having a detect output terminal, said detector circuit responsive to a predetermined characteristic in said downlink signal to assert a detect output signal on said detect output terminal; a clock, having a clock output terminal for presenting a clock output signal thereon; a counter, having a clock input terminal coupled to said clock output terminal, said counter having a plurality of counter output terminals for presenting a count value thereon, said counter responsive to cycles of said clock signal to increment said count value; a state register, having a plurality of bit storage locations therein, said state register having a plurality of state input terminals and a plurality of state output terminals; a data storage circuit comprising a plurality of bit storage locations, said data storage circuit having a store input terminal and a data input terminal for receiving a data input signal, said data storage circuit responsive to assertion of said store input to store data corresponding to said data input signal; a comparator circuit, having a match output terminal, and further having a first plurality of input terminals coupled to said data storage circuit and a second plurality of input terminals coupled to said counter output terminals, said comparator circuit responsive to a match between uplink telemetry data stored in said data storage circuit and said counter value to assert a signal on said match output terminal; a logic array, having; a plurality of logic array state input terminals coupled to said state register state output terminals; a plurality of logic array state output terminals coupled to said state register state input terminals; a plurality of counter input terminals coupled to said counter output terminals; a detect input terminal coupled to said detect output terminal; a match input terminal coupled to said comparator match output terminal; a downlink telemetry output terminal, coupled to said telemetry driver circuit input terminal to present said telemetry out signal thereto; an uplink telemetry output terminal, coupled to said telemetry driver input terminal; a store output terminal, coupled to said store input terminal of said data storage circuit; wherein said logic array is responsive to a first predetermined combination of signals applied to said state input terminals, counter input terminals, detect input terminal and match input terminal to assert signals on said store and said downlink telemetry output terminals, and wherein said logic array is responsive to a second predetermined combination of signals applied to said state input terminals, counter input terminals, detect input terminal, and match input terminal to assert a signal on said uplink telemetry output terminal.
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23. A telemetry system for communicating digital information via a radio-frequency signal, comprising:
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an antenna, adapted to receive said radio-frequency signal; an RF detect circuit, coupled to said antenna and responsive to said radio frequency signal to convert said radio-frequency signal into a digital pulse stream; a counting circuit, coupled to said RF detect circuit to receive said digital pulse stream, said counting circuit adapted to present a plurality of count value output signals representing a count value at a plurality of output terminals thereof, said counting circuit responsive to a first predetermined characteristic of said digital pulse stream to begin incrementing said count value at a predetermined rate and responsive to a second predetermined characteristic of said digital pulse stream to cease incrementing said counter value; a logic array, coupled to said counting circuit output terminals to receive said count value output signals, and coupled to said RF detect circuit to receive said digital pulse stream, said logic array responsive to a first predetermined combination of said counter value output signals and said digital pulse stream to assert a first output signal indicative of a digital "1" encoded into said radio-frequency signal, said logic array responsive to a second predetermined combination of said counter value output signals and said digital pulse stream to assert a second output signal indicative of a digital "0" encoded into said radio-frequency signal. - View Dependent Claims (24, 25, 26, 27)
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Specification