Method of doping a group III-V compound semiconductor

• US 5,350,709 A
• Filed: 06/10/1993
• Issued: 09/27/1994
• Est. Priority Date: 06/13/1992
• Status: Expired due to Fees

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Yamada, Takashi, Terada, Satoshi, Matsushita, Shigeharu, Kurose, Takashi, Nagamatsu, Akihito, Higashino, Takayoshi, Matsumura, Kouji, Fujii, Emi, Harada, Yasoo, Inoue, Daijirou
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/075,232
• Time in Patent Office: 474 Days
• Field of Search: 437/133, 437/160, 437/161, 437/987, 148/DIG. 34, 148/DIG. 65
• US Class Current: 438/181
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/22 Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
• CPC Class Codes: H01L 21/2258 Diffusion into or out of AIIIBV compounds
• CPC Class Codes: H01L 21/28587 characterised by the sectional shape, e.g. T, inverted T
• CPC Class Codes: H01L 21/28593 asymmetrical sectional shape
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/3245 of AIIIBV compounds
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/0891 of field-effect transistors with Schottky gate
• CPC Class Codes: H01L 29/1025 Channel region of field-effect devices
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/66075 of devices having semiconductor bodies comprising group 14 or group 13/15 materials comprising semiconducting carbon H01L29/66015; comprising crystalline silicon carbide H01L29/66053
• CPC Class Codes: H01L 29/66196 with an active layer made of a group 13/15 material
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66469 : with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/66856 : with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66871 : Processes wherein the final gate is made after the formation of the source and drain regions in the active layer, e.g. dummy-gate processes
• CPC Class Codes: H01L 29/66878 : Processes wherein the final gate is made before the formation, e.g. activation anneal, of the source and drain regions in the active layer
• CPC Class Codes: H01L 29/66977 : Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7787 : with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/812 : with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802
• CPC Class Codes: H01L 29/8122 : Vertical transistors SIT, PBT H01L29/7722
• CPC Class Codes: H01L 29/8605 : Resistors with PN junctions
• CPC Class Codes: Y10S 148/034 : Diffusion of boron or silicon
• CPC Class Codes: Y10S 438/962 : Quantum dots and lines

Abstract

A method of doping a Group III-V compound semiconductor with an impurity, wherein after an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed in this order on a crystal of Group III-V compound semiconductor, the sample is subjected to at least one heat treatment to cause silicon in the SiOx film to diffuse into the Group III-V compound semiconductor, thereby forming a doped layer. Using this doped layer forming method, field-effect transistors, diodes, resistive layers, two-dimensional electron gas or one-dimensional quantum wires, zero-dimensional quantum boxes, electron wave interference devices, etc. are fabricated.

Claims

1. A method of doping a Group III-V compound semiconductor with an impurity, comprising the steps of:

successively depositing on a crystal of a Group III-V compound semiconductor an undoped silicon oxide film (an SiOx film) and a film for preventing the external diffusion of Group V atoms that constitute part of the crystal of the Group III-V compound semiconductor; and

performing at least one heat treatment on the thus prepared sample to cause silicon (Si) in the SiOx film to diffuse into the Group III-V compound semiconductor.

2. A method of doping according to claim 1, wherein

the Group III-V compound semiconductor comprises at least one material selected from the group consisting of GaAs system, InP system, AlAs system, AlGaAs system, InGaAs system, and InAlAs system.

3. A method of doping according to claim 1, wherein

the film for preventing the external diffusion of Group V atoms is at least one selected from the group consisting of an SiN film, an AlN film, a WSi film, and a WSiN film.

4. A method of doping according to claim 1, wherein

x in the SiOx film is less than 2.

5. A method of doping according to claim 1, further comprising the step of:

after depositing the two films, leaving the two films in a designated region unremoved or leaving the film for preventing the external diffusion of Group V atoms in a designated region and the SiOx film unremoved.

6. A method of doping according to claim 1, wherein

when depositing the two films, the thickness and/or properties of at least either one of the films are varied to modify the diffusion profile of Si after heat treatment.

7. A method of fabricating a field-effect transistor having a lightly doped layer formed directly below a gate electrode, a highly doped layer forming a source and a drain region, and a moderately doped layer formed between the lightly doped and highly doped layers, the three layers being formed at the surface of a substrate of a Group III-V compound, comprising the steps of:

forming the lightly doped layer at the surface of the substrate;

forming the gate electrode on the center portion of the upper surface of the lightly doped layer;

forming an undoped SiOx film and a Group V atom diffusion stop film over the upper surface of the lightly doped layer;

forming the highly doped layer at each end of the lightly doped layer;

forming by heat treatment the moderately doped layer in the lightly doped layer except the portion thereof directly below the gate electrode; and

forming an ohmic electrode on the upper surface of the highly doped layer.

8. A method of fabricating a field-effect transistor on a Group III-V compound semiconductor substrate, comprising the steps of:

selectively etching the compound semiconductor substrate in a substantially vertical direction;

forming a composite film consisting of an undoped SiOx film and a Group V atom diffusion stop film over the horizontal and vertical surfaces of the selectively etched compound semiconductor substrate;

forming an active layer by heat-treating the compound semiconductor substrate with the composite film formed thereon and by diffusing Si into the compound semiconductor substrate;

forming a source electrode and a drain electrode on the active layer formed on the horizontal surface of the compound semiconductor substrate; and

forming a gate electrode on the active layer formed on the vertical surface of the compound semiconductor substrate.

9. A method of fabricating a field-effect transistor having an active layer and an impurity-diffused layer formed in a Group III-V compound semiconductor substrate, with a gate electrode formed on the active layer and a source electrode and a drain electrode formed on the impurity-diffused layer, comprising the steps of:

forming a stepped portion by etching the Group III-V compound semiconductor substrate;

forming the active layer in the upper part of the stepped portion;

forming a composite film consisting of an undoped SiOx film and a Group V atom diffusion stop film on the side and lower parts of the stepped portion of the compound semiconductor substrate; and

forming the impurity-diffused layer by heat-treating the compound semiconductor substrate with the composite film formed thereon and by diffusing Si into the compound semiconductor substrate.

10. A method of forming a field-effect transistor having a plurality of doped layers of different impurity concentrations formed in a Group III-V compound semiconductor substrate, comprising the steps of:

forming an undoped SiOx film and a Group V atom diffusion stop film in this order on the Group III-V compound semiconductor substrate;

forming a doped layer by diffusing Si into the Group III-V compound semiconductor substrate by heat treatment;

removing the SiOx film and the he Group V atom diffusion stop film in a designated region; and

performing heat treatment again and forming, in a region covered by the SiOx film and the Group V atom diffusion stop film, a doped layer having a higher impurity concentration than the first formed doped layer.

11. A method of fabricating a semiconductor circuit device having conductive layers of different resistivities by doping a Group III-V compound semiconductor with an impurity, comprising the steps of:

forming an undoped SiOx film and a Group V atom diffusion stop film in this order on the Group III-V compound semiconductor;

reducing the thickness of the Group V atom diffusion stop film over a region where a conductive layer of higher resistivity is to be formed; and

diffusing Si into the Group III-V compound semiconductor by heat-treating the Group III-V compound semiconductor.

12. A method of fabricating a semiconductor circuit device having conductive layers of different resistivities by doping a Group III-V compound semiconductor with an impurity, comprising the steps of:

constructing a heterojunction layer by forming a wide-gap semiconductor layer on an undoped narrow-gap semiconductor layer which is the Group III-V compound semiconductor;

forming an undoped SiOx film and a Group V atom diffusion stop film in this order on the heterojunction layer;

reducing the thickness of the Group V atom diffusion stop film over a region where a conductive layer of higher resistivity is to be formed; and

diffusing Si into the Group III-V compound semiconductor by heat-treating the Group III-V compound semiconductor.

13. A method of fabricating a field-effect transistor having a doped layer formed in a Group III-V compound semiconductor layer as a channel layer or an electron supply layer, comprising the steps of:

forming an undoped SiOx film and a Group V atom diffusion stop film in this order on the Group III-V compound semiconductor layer;

forming the doped layer by diffusing Si into the Group III-V compound semiconductor layer by heat treatment; and

subjecting the doped layer to heat treatment and causing Si in the doped layer to further diffuse into the Group III-V compound semiconductor layer to increase the thickness of the doped layer.

14. A method of forming a one-dimensional or two-dimensional electric conductive region by diffusing an impurity into a Group III-V compound semiconductor, comprising the steps of:

forming an undoped SiOx film and a Group V atom diffusion stop film in this order on the Group III-V compound semiconductor;

removing the Group V diffusion stop film everywhere except where the electric conductive region is to be formed; and

diffusing Si into the Group III-V compound semiconductor by heat treatment.

15. A method of forming a quantum wire, comprising the steps of:

forming an Si diffusion stop layer on a Group III-V compound semiconductor substrate and thereby forming a step;

forming an undoped SiOx film and a Group V atom diffusion stop film in this order on the substrate and the Si diffusion stop layer;

removing the SiOx film and the Group V atom diffusion stop film everywhere except the portions thereof formed on the sidewall of the step; and

heating the thus processed substrate and thereby causing Si to diffuse from the SiOx film into the Group III-V compound semiconductor substrate across their interface, to form a quantum wire.

16. A method of forming a quantum wire, comprising the steps of:

forming all undoped SiOx film and a Group V atom diffusion stop film in this order on the surface of a substrate consisting of a plurality of dissimilar Group III-V compound semiconductors that are joined side by side to form the surface of the substrate;

forming diffused areas of different depths in the Group III-V compound semiconductors by diffusing Si from the SiOx film by heat treatment; and

removing the surface portion of the substrate so that the deeper diffused area remains in the substrate, and forming a quantum wire by a one-dimensional electron gas that occurs near the remaining diffused area.

17. A method of forming a quantum wire in which the moving direction of carriers in a channel layer is one dimensional, comprising the steps of:

forming successively a narrow-gap semiconductor layer and a wide-gap semiconductor layer, both of Group III-V compound semiconductors, in this order on a substrate;

forming the wide-gap semiconductor layer into a sawtooth-like cross section using an etching technique that utilizes the dependence of etching on the surface orientation of the wide-gap semiconductor layer;

forming an undoped SiOx film and a Group V atom diffusion stop film in this order on the wide-gap semiconductor layer formed in a sawtooth shape;

forming a doped layer by performing heat treatment and diffusing Si into the surface of the wide-gap semiconductor layer; and

forming a channel layer, and hence a quantum wire, only in the region of the narrow-gap semiconductor layer that lies directly below each trough of the sawtooth-shaped doped layer.

18. A method of forming a quantum box that confines carriers in a channel layer into a three-dimensional space, comprising the steps of:

forming successively a narrow-gap semiconductor layer and a wide-gap semiconductor layer, both of Group III-V compound semiconductors, in this order on a substrate;

forming the wide-gap semiconductor layer into a sawtooth shape using an etching technique that utilizes the dependence of etching on the surface orientation of the wide-gap semiconductor layer;

forming an undoped SiOx film on the wide-gap semiconductor layer formed in a sawtooth shape;

forming a Group V atom diffusion stop layer over a region where a quantum box is to be formed;

forming a doped layer by performing heat treatment and diffusing Si into a designated region of the surface of the wide-gap semiconductor layer; and

forming a channel layer, and hence a quantum box, only in the region of the narrow-gap semiconductor layer that lies directly below each trough of the sawtooth structure and that is covered by the doped layer.

19. A method of fabricating a semiconductor circuit device having on a substrate a diffused layer containing areas of different impurity concentrations, with electrodes formed on the diffused layers, comprising the steps of:

forming a Group III-V compound semiconductor layer on a substrate;

forming on the semiconductor layer a plurality of shields, of different shielding widths, spaced apart by a prescribed distance;

forming an undoped SiOx film and a Group V atom diffusion stop film in this order over the surfaces of the shields and the semiconductor surface except for the shields; and

forming diffused layers by diffusing Si into the semiconductor layer by heat treatment.

20. A method of fabricating a semiconductor integrated circuit by doping a Group III-V compound semiconductor with an impurity and forming a plurality of devices, comprising the steps of:

forming an undoped narrow-gap semiconductor layer and a wide-gap semiconductor layer, both of Group III-V compound semiconductors, in this order on a substrate, thus constructing a heterojunction layer;

exposing the narrow-gap semiconductor layer by removing the wide-gap semiconductor layer in a designated region;

forming an undoped SiOx film and a Group V atom diffusion stop film in this order over the narrow-gap semiconductor layer and the wide-gap semiconductor layer;

forming doped layers by diffusing Si into the Group III-V semiconductor by heat treatment; and

forming electrodes on the doped layers.

21. A method of fabricating a semiconductor integrated circuit by doping a Group III-V compound semiconductor with an impurity and forming a plurality of devices, comprising the steps of:

forming an undoped narrow-gap semiconductor layer and a wide-gap semiconductor layer, both of Group III-V compound semiconductors, in this order on a substrate, thus constructing a heterojunction layer;

partially removing the wide-gap semiconductor layer in the direction of its depth in a designated region;

forming an SiOx film and a Group V atom diffusion stop film over the wide-gap semiconductor layer having a varying thickness;

forming doped layers by diffusing Si into the Group III-V semiconductor by heat treatment; and

forming electrodes on the doped layers.