Chip identification scheme

• US 5,350,715 A
• Filed: 11/12/1992
• Issued: 09/27/1994
• Est. Priority Date: 11/12/1991
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Wui-soo
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Picardat, Kevin M.
• Application Number:
  US07/974,423
• Time in Patent Office: 684 Days
• Field of Search: 437/250, 437/8, 437/7, 437/935, 437/924, 148/DIG. 162
• US Class Current: 438/16
• CPC Class Codes: H01L 2223/54413 comprising digital information, e.g. bar codes, data matrix
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/975 Substrate or mask aligning feature

Abstract

A method for determining the original location of each of a multiplicity of semiconductor chips fabricated on a common wafer, including the step of applying location identification data to each of the chips, wherein the location identification data is indicative of the original location of the chip on the wafer. The applying step is preferably performed during the process for fabricating the chips on the wafer, for example, by means of using a photomask in a conventional photolithographic process to etch a location identification mark on a predetermined layer of each chip. The location identification mark can be, for example, a dot matrix pattern which signifies the original location of the chip to which it is affixed on the wafer on which it was fabricated, in accordance with a binary coding scheme. The location identification data can be detected or read from any of the chips even after they are separated from the wafer, to thereby facilitate wafer fabrication process control, by facilitating the determination of the original wafer location of any chips which are found to be defective.

Claims

1. A method for determining the original location of a semiconductor chip fabricated on a wafer, comprising the step of applying a location identification mark on the chip, said location identification mark being indicative of the original location of the chip on the wafer, said location identification mark being comprised of a plurality m of rows of binary indicia and a plurality n of columns of binary indicia arranged in an m x n matrix, wherein a total coded value for said matrix is calculated by summing total row values calculated for each row by multiplying a row value assigned to that row by the sum of column values assigned to each column in that row where a "1" bit is present.

2. The method as set forth in claim 1, further comprising the step of detecting said location identification mark after the chip is separated from the wafer.

3. The method as set forth in claim 2, further comprising the step of determining the original location of the chip on the wafer in response to said detecting step.

4. The method as set forth in claim 1, wherein said applying step is performed during the process for fabricating the chip on the wafer.

5. The method as set forth in claim. 1, wherein said applying step is carried out by means of a photolithographic process performed during the process for fabricating the chip on the wafer.

6. The method as set forth in claim 5, wherein said photolithographic process is performed by means of using a photomask having a dot matrix pattern to etch a corresponding matrix pattern of contact holes in a layer of the chip.

7. The method as set forth in claim 6, wherein said corresponding matrix pattern occupies a relatively small portion of the total area of a surface of said layer of the chip.

8. The method as set forth in claim 1, wherein said patterned indicia include an additional row having a total row value which serves as a position reference for facilitating alignment of a detection means for detecting said indicia.