High voltage structures with oxide isolated source and resurf drift region in bulk silicon

• US 5,350,932 A
• Filed: 12/17/1993
• Issued: 09/27/1994
• Est. Priority Date: 03/26/1992
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Malhi, Satwinder
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/169,731
• Time in Patent Office: 284 Days
• Field of Search: 357/23.4, 357/23.6, 357/23.7, 257/51, 257/67, 257/318, 257/394, 257/401
• US Class Current: 257/67
• CPC Class Codes: H01L 29/78639 with a drain or source connected to a bulk conducting substrate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate

Abstract

An integrated circuit RESURF LDMOS power transistor employs a source isolated, embedded gate MOS transistor with RESURF LDMOS technology to provide a source isolated high voltage power transistor with low "on" resistance for use in applications requiring electrical isolation between the source and substrate.

Claims

1. A high voltage power transistor, comprising:

a source isolated, embedded gate MOS transistor having a gate region formed in a semiconductor substrate, and having a source region, a drain region, and a channel region, wherein the source region and the drain region are separated by the channel region which is located above the gate region and the source region, drain region and channel region overlie an insulating layer covering a portion of the substrate; and

a bulk semiconductor drain drift region connected to the drain region through an opening in the insulating layer of the source isolated, embedded gate MOS transistor.

2. The high voltage power transistor of claim 1 wherein the source isolated, embedded gate MOS transistor comprises:

a substrate of semiconductor material;

a diffusion formed in the substrate whereby a gate isolation diffusion is formed;

a second diffusion of higher doping concentration than the gate isolation diffusion formed in the gate isolation diffusion whereby a gate diffusion is formed;

an insulating layer overlying the source isolated, embedded gate transistor whereby a gate oxide is formed over the gate diffusion; and

a semiconductor layer deposited over the insulating layer having three sections, one section forming a source for both the source isolated, embedded gate MOS transistor and the high voltage power transistor, a second section forming a channel, and a third section forming a drain.

3. The source isolated, embedded gate MOS transistor of claim 2 wherein the substrate and the channel are composed of P type semiconductor material, the gate isolation diffusion is composed of N- type semiconductor material, and the gate diffusion, source, and drain are composed of N+ type semiconductor material.

4. The source isolated, embedded gate MOS transistor of claim 2 wherein the substrate, gate isolation diffusion, gate diffusion, and semiconductor layer having three sections are composed of single crystal silicon.

5. The source isolated, embedded gate MOS transistor of claim 2 wherein the semiconductor layer having three sections is composed of polycrystalline silicon.

6. The source isolated, embedded gate transistor of claim 2 wherein the insulating layer overlying the substrate is either silicon dioxide, silicon nitride, or a combination of silicon dioxide and silicon nitride.

7. The high voltage power transistor of claim 1 wherein the drain drift region comprises:

a substrate of semiconductor material;

a diffusion in the substrate whereby a drift region is formed;

a first diffusion, inside the drift region, of higher doping concentration than the drift region whereby a drain contact region is formed;

a second diffusion, spaced from the first diffusion and inside the drift region, of higher doping concentration than the drift region whereby a drain drift region contact is formed;

a patterned insulating layer overlying the drain drift region with openings for contact down to the first and second diffusions inside the drift region; and

a patterned conductive layer making electrical contact to both the second diffusion inside the drift region and to a drain of the source isolated, embedded gate transistor.

8. The drain drift region of claim 7 wherein the substrate is P type semiconductor material, the drift region is N type semiconductor material, and both first and second diffusions inside the drift region are N+ type semiconductor material.

9. The drain drift region of claim 8 wherein the P type substrate doping concentration and the N type drift region depth and doping profile are designed according to RESURF design principles such that the drift region fully depletes at or before rated breakdown voltage of the high voltage power transistor.

10. The high voltage power transistor of claim 1 wherein the drain drift region comprises:

a substrate of semiconductor material;

a diffusion in the substrate whereby a drift region is formed;

a first diffusion, inside the drift region, of higher doping concentration than the drift region whereby a drain contact region is formed;

a second diffusion, spaced from the first diffusion and inside the drift region, of higher doping concentration than the drift region whereby a drain drift region contact is formed;

a patterned insulating layer overlying the drain drift region with openings for contact down to the first and second diffusions inside the drift region; and

a patterned conductive layer overlying the patterned insulating layer having two sections, one section making electrical contact to both the second diffusion inside the drift region and to a drain of the source isolated, embedded gate transistor, and a second section lying between the first and second diffusions inside the drift region whereby a field plate is formed.

11. The drain drift region of claim 10 wherein the substrate is P type semiconductor material, the drift region is N type semiconductor material, and the first and second diffusions inside the drift region are N+ type semiconductor material.

12. The drain drift region of claim 10 wherein the conductive layer is electrically connected to either source, gate, or drain terminal of the source isolated, embedded gate transistor, or is held at a potential below that of the drain terminal of the high voltage power device.

13. The drain drift region of claim 10 wherein the P type substrate doping concentration and the N type drift region depth and doping profile are designed according to RESURF design principles such that the drift region fully depletes at or before rated breakdown voltage of the high voltage power transistor.

14. A high voltage power transistor with electrical isolation between source and substrate, comprising:

a drain drift region formed in a semiconductor substrate having a drain contact and an interconnect contact; and

a source isolated, embedded gate MOS transistor having a source region formed on an insulating layer overlying the substrate, a drain region forming a drain interconnect formed on the insulating layer, the source region and the drain region separated by a channel region that also overlies the insulating layer, a gate region formed in the substrate and located below the channel, a source contact connected to the source region, a gate contact connected to the gate region through an opening in the channel and the insulating layer, and the drain interconnect connected to the interconnect contact of the drain drift region through an opening in the insulating layer.

15. A high side driver configuration with a high voltage power transistor having its source region isolated from the substrate, comprising:

a drain drift region formed in a semiconductor substrate having a drain contact and an interconnect contact with the drain contact connected to a power supply; and

a source isolated, embedded gate MOS transistor having a source region formed on an insulating layer overlying the substrate, a drain region forming a drain interconnect formed on the insulating layer, the source region and drain region separated by a channel region that also overlies the insulating layer, a gate region formed in the substrate and located below the channel, a source contact connected to the source region, a gate contact connected to the gate region through an opening in the channel and the insulating layer, and the drain interconnect connected to the interconnect contact of the drain drift region through an opening in the insulating layer.