Macrocell with flexible product term allocation

• US 5,350,954 A
• Filed: 03/29/1993
• Issued: 09/27/1994
• Est. Priority Date: 03/29/1993
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Patel, Rakesh H.
• Primary Examiner(s): Hudspeth, David R.
• Application Number:
  US08/039,927
• Time in Patent Office: 547 Days
• Field of Search: 307/443, 307/243, 307/465-469
• US Class Current: 326/39
• CPC Class Codes: H03K 19/1736 in which the wiring can be modified
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence

Abstract

An improved macrocell is provided for summing product term inputs to complete a sum of products. Some or all of a macrocell'"'"'s product terms can be allocated to another macrocell. The macrocell OR function remains available to sum product term inputs, even when other product term inputs in the same macrocell are allocated elsewhere. Macrocells can also by daisy-chained bidirectionally, so that the delay associated with allocating product terms between multiple macrocells can be reduced.

Claims

1. Programmable logic array apparatus comprising a plurality of macrocells each of which receives a finite number of multiple input signals, each macrocell comprising:

a first logic gate for producing a first logical function of a first number of the input signals, the first number being from zero to the finite number;

a second logic gate for producing a second logical function of a second number of the input signals, the second number being from zero to the finite number, such that the first number added to the second number is finite number; and

allocation logic for receiving the first logical function of the first number of input signals from the first logic gate and allocating the first logical function of the first number of input signals to another macrocell, wherein when the first logical function of a first macrocell is allocated to a second macrocell, the first logic gate of the second macrocell receives the first logical function of the first macrocell the second logical function of the first macrocell is retained by the first macrocell.

2. The apparatus defined in claim 1 further comprising:

register logic capable of storing a selected one of (a) the first logical function of the first number of input signals, and (b) the second logical function of the second number of input signals.

3. The apparatus defined in claim 2 further comprising:

a local feedback connection that is connected to the register logic.

4. The apparatus defined in claim 1 wherein the input signals are product terms.

5. The apparatus defined in claim 1 wherein the first logic gate is an OR gate for summing the first number of input signals, the first logical function being the sum of the first number of input signals.

6. The apparatus defined in claim 1 wherein the second logic gate is an OR gate for summing the second number of input signals, the second logical function being the sum of the second number of input signals.

7. The apparatus defined in claim 1 wherein the allocation logic comprises:

means for allocating the first logical function to a first additional macrocell; and

means for allocating the first logical function to a second additional macrocell, the second additional macrocell being distinct from the first additional macrocell.

8. A macrocell that receives a plurality of input signals, comprising:

a first logic gate for producing a first function of a first number of the input signals;

a second logic gate for producing a second logical function of a second number of the input signals; and

allocation logic for receiving the function of the first number of input signals from logic gate and allocating the first logical function of the first number of input signals to another macrocell, wherein the allocation logic comprises;

a first multiplexer for receiving the first logical function of the first number of input signals, the first multiplexer being connected to the first additional macrocell for directing a selected one of (a) a logic low and (b) the first logical function of the first number of input signals to a first additional macrocell; and

a second multiplexer for receiving the first, logical function of the first number of input signals, the second multiplexer being connected to the second additional macrocell for directing a selected one of (a) a logic low and (b) the first logical function of the first number of input. signals to a second additional macrocell.

9. A macrocell that receives a plurality of input signals, comprising:

a first logic gate for producing a first logical function of a first number of the input signals;

a second logic gate for producing a second logical function of a second number of the input signals;

allocation logic for receiving the first logical function of the first number of input signals from the first logic gate and allocating the first logical function of the first number of input signals to another macrocell;

means for selectively directing the first number of input signals to the first logic gate; and

means for selectively directing the second number of input signals to the second logic gate, the second number of input signals and the first number of signals being mutually exclusive.

10. Programmable logic array apparatus comprising a plurality of macrocells, each macrocell receiving a finite number of multiple input signals, the apparatus comprising:

a first macrocell, comprising;

a first logic gate for providing a first logical function of a first number of input signals, the first number being from zero to the finite number;

means for allocating the first number of input signals to a second macrocell distinct from the first macrocell; and

means for allocating the first number of input signals to a third macrocell, the third macrocell being distinct from the first and second macrocells.

11. The apparatus defined in claim 10 further comprising:

register logic capable of storing a selected one of (a) the first logical function of the first number of input signals and (b) the second logical function of the second number of input signals.

12. The apparatus defined in claim 11 further comprising:

a local feedback connection that is connected to the register logic.

13. The apparatus defined in claim 10 further comprising:

a second logic gate for providing a second logical function of a second number of input signals.

14. The apparatus defined in claim 13 wherein the second logic gate is an OR gate for summing the second number of input signals, the second logical function being the sum of the second number of input signals.

15. The apparatus defined in claim 10 wherein the input signals are product terms.

16. The apparatus defined in claim 10 wherein the first logic gate is an OR gate for summing the first number of input signals, the first logical function being the sum of the first number of input signals.

17. A macrocell for receiving a plurality of input signals, comprising:

a first logic gate for providing a first logical function of a first number of input signals;

means for allocating the first number of input signals to a first additional macrocell; and

means for allocating the first number of input signals to a second additional macrocell, the second additional macrocell being distinct from the first additional macrocell, wherein the means for allocating the first number of input signals to the first additional macrocell comprises;

a first multiplexer for receiving the first number of input signals, the first multiplexer being connected to the first additional macrocell for directing a selected one of (a) a logic low and (b) the first number of input signals to the first additional macrocell.

18. The macrocell defined in claim 17 wherein the means for allocating the first number of product terms to the second additional macrocell comprises:

a second multiplexer for receiving the first number of input signals, the second multiplexer being connected to the second additional macrocell for directing a selected one of (a) a logic low and (b) the first number of input signals to the second additional macrocell.

19. A macrocell for receiving a plurality of input signals, comprising:

a first logic gate for providing a first logical function of a first number of input signals;

means for allocating the first number of input signals to a first additional macrocell;

means for allocating the first number of input signals to a second additional macrocell, the second additional macrocell being distinct from the first additional macrocell;

means for selectively directing the first number of input signals to the first logic gate; and

means for selectively directing the second number of input signals to the second logic gate, the second number of input signals and the first number of input signals being mutually exclusive.

20. A method of allocating product terms between macrocells comprising the steps of:

providing a first logical function of a first number of input signals with a first logic gate;

providing a second logical function of a second number of input signals with a second logic gate;

allocating the first number of input signals to a first macrocell; and

allocating the first number of input signals to a second macrocell, the second macrocell being distinct from the first macrocell, wherein the step of allocating the first number of input signals to the first macrocell further comprises the steps of;

receiving the first number of input signals with a first multiplexer that is connected to the first macrocell; and

directing through the first multiplexer a selected one of (a) a logic low and (b) the first number of input signals to the first macrocell.

21. The method defined in claim 20 wherein the step for allocating the first number of input signals to the second macrocell further comprises the steps of:

receiving the first number of input signals with a second multiplexer that is connected to the second macrocell; and

directing through the second multiplexer a selected one of (a) a logic low and (b) the first number of input signals to the second macrocell.

22. The method defined in claim 20 further comprising the step of:

storing a selected one of (a) the first logical function of the first number of input signals and (b) the second logical function of the second number of logical functions with register logic.

23. The method defined in claim 20 further comprising the step of:

providing a local feedback connection that is connected to the register logic.

24. The method defined in claim 20 wherein the step of providing the first logical function comprises the step of:

summing the first input signals with the first logic gate, the first logic gate being an OR gate.

25. The method defined in claim 20 wherein the step of providing the second logical function comprises the step of:

summing the second input signals with the second logic gate, the second logic gate being an OR gate.

26. The method defined in claim 20 wherein the input signals are product terms.

27. The method of claim 20 further comprising the steps of:

selectively directing the second number of input signals to the first logic gate; and

selectively directing the second number of input signals to the second logic gate, the second number of input signals and the first number of input signals being mutually exclusive.

28. A method of allocating input signals between macrocells comprising the steps of:

providing a first logical function of a first number of input signals with a first logic gate;

allocating the first number of signals to a first macrocell;

allocating the first number of input signals to a second macrocell, the second macrocell being distinct from the first macrocell;

selectively directing the first number of input signals to the first logic gate; and

selectively directing the second number of input signals to the second logic gate, the second number of input signals and the first number of input signals being mutually exclusive.

29. The method defined in claim 28 further comprising the steps of:

providing a second logical function of a second number of inputs with a second logic gate.

30. The method defined in claim 29 wherein the step of providing the second logical function comprises the step of:

summing the second input signals with the second logic gate, the second logic gate being an OR gate.

31. The method defined in claim 28 further comprising the step of:

receiving the second number of inputs with register logic.

32. The method defined in claim 31 further comprising the step of:

providing a local feedback connection that is connected to the register logic.

33. The method defined in claim 28 wherein the step of allocating the first number of input signals to the first macrocell further comprises the steps of:

receiving the first number of input signals with a first multiplexer that is connected to the first macrocell; and

directing through the first multiplexer a selected one of (a) a logic low and (b) the first number of input signals to the first macrocell.

34. The method defined in claim 33 wherein the step of allocating the first number of input signals to the second macrocell further comprises the steps of:

receiving the first number of input signals with a second multiplexer that is connected to the second macrocell; and

directing through the second multiplexer a selected one of (a) a logic low and (b) the first number of input signals to the second macrocell.

35. The method defined in claim 28 wherein the step of providing the first logical function comprises the step of:

summing the first input signals with the first logic gate, the first logic gate being an OR gate.

36. Programmable logic array apparatus comprising:

a plurality of macrocells, each of which includes (a) a plurality of first means, each of which is capable of producing an associated intermediate output signal which is an associated selected logical function of a plurality of input signals, and (b) second means capable of producing a final output signal which is a selected logical function of said intermediate output signals, the second means of at least one of said macrocells further including;

third means capable of producing a further intermediate output signal which is a selected logical function of at least some of said intermediate output signals; and

fourth means for selectively applying either said final output signal or said further intermediate output signal to the second means of at least one other macrocell for use by the second means of that other macrocell as an intermediate output signal.

37. The apparatus defined in claim 36 wherein said fourth means comprises:

fifth means for selectively applying either said final output signal or said further intermediate output signal to the second means of a first other macrocell for use by the second means of said first other macrocell as an intermediate output signal; and

sixth means for selectively applying either said final output signal or said further intermediate output signal to the second means of a second other macrocell for use by the second means of said second other macrocell as an intermediate output signal.

38. The apparatus defined in claim 36 wherein said second means of said one of said macrocells comprises first logic circuitry capable of receiving substantially all of said intermediate output signals and for producing said final output signal from the intermediate output signals received by said first logic circuitry, and wherein said third means comprises second logic circuitry capable of receiving substantially less than all of said intermediate output signals and for producing said further intermediate output signal from the intermediate output signals received by said second logic circuitry.

39. The apparatus defined in claim 36 wherein, in addition to said one of said macrocells, the second means of at least one other of said macrocells includes third and fourth means similar to the third and fourth means of said one of said macrocells, wherein the fourth means of said one other of said macrocells selectively applies either the final output signal or the further intermediate output signal of said one other of said macrocells to the second means of said one of said macrocells, and wherein said second means of said one of said macrocells is capable of using said final output signal or said further intermediate output signal of said one other of said macrocells as an intermediate output signal.

40. The apparatus defined in claim 39 wherein, in addition to said one and said one other of said macrocells, the second means of a third of said macrocells includes third and fourth means similar to the third and fourth means of said one of said macrocells, wherein the fourth means of said third of said macrocells selectively applies either the final output signal or the further intermediate output signal of said third of said macrocells to the second means of said one of said macrocells, and wherein said second means of said one of said macrocells is capable of using said final output signal or said further intermediate output signal of said third of said macrocells as an intermediate output signal.

41. The apparatus defined in claim 40 wherein said one of said macrocells is disposed on said programmable logic array intermediate said one other and said third of said macrocells.

42. The apparatus defined in claim 36 wherein said one of said macrocells further comprises:

register means for selectively storing a signal applied to said register means as a data signal; and

switching means for directing a selected one of (a) said final output signal and (b) said further intermediate output signal to said register means as said data signal.

43. The apparatus defined in claim 36 wherein said one of said macrocells further comprises:

a macrocell output terminal; and

switching means for directing a selected one of (a) said final output signal and (b) said further intermediate output signal to said macrocell output terminal.

44. The apparatus defined in claim 36 wherein said one of said macrocells further comprises:

register means for selectively storing a signal applied to said register means as a data signal and for producing a register output signal indicative of the signal stored by said register;

a macrocell output terminal;

first switching means for applying either said final output signal or said further intermediate output signal to said register means as said data signal; and

second switching means for applying either said data signal or said register output signal to said macrocell output terminal.

45. The apparatus defined in claim 36 wherein said one of said macrocells further comprises:

register means for selectively storing a signal applied to said register means as a data signal; and

switching means for selectively applying one of (a) an intermediate output signal, (b) said final output signal, and (c) said further intermediate output signal to said register means as said data signal.

46. The apparatus defined in claim 45 wherein said register means produces a register output signal which is indicative of the signal stored by said register means, and wherein said one of said macrocells further comprises:

a macrocell output terminal; and

further switching means for selectively applying either said data signal or said register output signal to said macrocell output terminal.