Lossless active snubber for half-bridge output rectifiers

• US 5,351,179 A
• Filed: 03/05/1993
• Issued: 09/27/1994
• Est. Priority Date: 03/05/1993
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Tsai, Fu Sheng, Dalal, Dhaval B.
• Primary Examiner(s): Sterrett, Jeffrey L.
• Application Number:
  US08/027,031
• Time in Patent Office: 571 Days
• Field of Search: 363/17, 363/44, 363/45, 363/46, 363/530, 363/84, 363/89, 363/126, 363/52, 363/127
• US Class Current: 363/53
• CPC Class Codes: H02M 1/342 Active non-dissipative snubbers
• CPC Class Codes: H02M 3/335 using semiconductor devices only
• CPC Class Codes: H02M 7/062 Avoiding or suppressing excessive transient voltages or currents
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A bridge-type primary switching circuit (12) is represented by a pulsed voltage source (VSW). The primary switched waveform is transformed to secondary circuit (14) using a transformer (T1) with the required turns ratio N and a center-tapped secondary winding (16). Half-bridge rectifier (18) formed by diodes (DR1) and (DR2) rectifies the secondary waveform and feeds the waveform through a low-pass filter (LF) and (CF) to obtain the desired DC output voltage. The snubber circuit (20) is represented by switch-diode-capacitor combinations (SA-DS1-CS1) and (SB-DS2-CS2) across each rectifier (DR1) and (DR2). Capacitances (CS1) and (CS2) are selected large enough such that their voltages remain essentially constant during a switching cycle. The controlled switches (SA) and (SB) are turned ON with a specific delay after the primary voltage reaches a magnitude close to the input voltage in order to allow the rectifier diodes (DR1) and (DR2) to be commutated. It is crucial that the switches (SA) and (SB) be turned OFF before the primary voltage collapses to zero to avoid current spikes through the switches.

Claims

1. A pulse width modulated direct current--direct current converter circuit, which comprises a bridge-type primary switching circuit having an input for a direct current at a first voltage and having an output supplying a chopped alternating current signal derived from the direct current, a transformer including a primary winding connected to the output of the primary circuit and a center-tapped secondary winding, a half-bridge rectifier including first and second rectifier diodes connected to each of two end terminals of said center-tapped secondary winding, and a snubber circuit connected across said first and second rectifier diodes, said snubber circuit including a first snubber diode connected in a reverse direction to said first rectifier diode, a first snubber capacitor serially connected to said first snubber diode, said first snubber diode and first snubber capacitor being connected across said first rectifier diode, a first controllable switch connected across said first snubber diode, a second snubber diode connected in a reverse direction to said second rectifier diode and a first control signal input connected to said first controllable switch to turn said first controllable switch ON during a maximum magnitude of a first polarity in a pulse of the chopped alternating current signal.

2. The pulse width modulated direct current - direct current converter circuit of claim 1 additionally comprising a second controllable switch connected across said second snubber diode and a second control signal input connected to said second controllable switch to turn said second controllable switch ON during a maximum magnitude of a second polarity opposite to the first polarity in a pulse of the chopped alternating current signal.

3. The pulse width modulated direct current--direct current converter circuit of claim 2 in which said first and second controllable switches each have current flow electrodes which are connected together and connected to said first snubber capacitor.

4. The pulse width modulated direct current--direct current converter circuit of claim 2 additionally comprising a second snubber capacitor serially connected to said second snubber diode, said second snubber diode and second snubber capacitor being connected across said second rectifier diode.

5. The pulse width modulated direct current--direct current converter circuit of claim 1 further comprising a low-pass filter connected to said first and second rectifier diodes, an output of said low-pass filter providing a direct current output at a second voltage.

6. The pulse width modulated direct current--direct current converter circuit of claim 1 in which said bridge-type primary switching circuit is a full-bridge pulse width modulated switching circuit.

7. The pulse width modulated direct current--direct current converter circuit of claim 6 in which said bridge-type primary switching circuit comprises second and third controllable switches connected between said input for the direct current and one end of said transformer primary winding, fourth and fifth controllable switches connected between said input for the direct current and another end of said transformer primary winding, a second and third control signal input connected to said second and third controllable switches to turn said second and third controllable switches ON during a maximum magnitude of a first polarity in a pulse of the chopped alternating current signal.

8. The pulse width modulated direct current--direct current converter circuit of claim 7 in which said first, second, third, fourth, and fifth controllable switches comprise metal oxide semiconductor field effect transistors.

9. The pulse width modulated direct current--direct current converter circuit of claim 7 in which the first control signal and the second control signal are generated from a common control signal by means of a first delay element for the first control signal and a second delay element for the second control signal.

10. A pulse width modulated direct current--direct current converter circuit, which comprises a bridge-type primary switching circuit having an input for a direct current at a first voltage and having an output supplying a chopped alternating current signal derived from the direct current, a transformer including a primary winding connected to the output of the primary circuit and a center-tapped secondary winding, a half-bridge rectifier including first and second rectifier diodes connected to each of two end terminals of said center-tapped secondary winding, and a snubber circuit connected across said first and second rectifier diodes, said snubber circuit including a first snubber diode connected in a reverse direction to said first rectifier diode, a first snubber capacitor serially connected to said first snubber diode, said first snubber diode and first snubber capacitor being connected across said first rectifier diode, a first controllable switch connected across said first snubber diode, a second snubber diode connected in a reverse direction to said second rectifier diode, a first control signal input connected to said first controllable switch to turn said first controllable switch ON during a maximum magnitude of a first polarity in a pulse of the chopped alternating current signal and a second controllable switch connected across said second snubber diode and a second control signal input connected to said second controllable switch to turn said second controllable switch ON during a maximum magnitude of a second polarity opposite to the first sign in a pulse of the chopped alternating current signal.

11. The pulse width modulated direct current--direct current converter circuit of claim 10 further comprising a low-pass filter connected to said first and second rectifier diodes, an output of said low-pass filter providing a direct current output at a second voltage.

12. The pulse width modulated direct current--direct current converter circuit of claim 10 in which said bridge-type primary switching circuit is a full-bridge pulse width modulated switching circuit.

13. The pulse width modulated direct current--direct current converter circuit of claim 12 in which said bridge-type primary switching circuit comprises third and fourth controllable switches connected between said input for the direct current and one end of said transformer primary winding, fifth and sixth controllable switches connected between said input for the direct current and another end of said transformer primary winding, a third and fourth control signal input connected to said third and fourth controllable switches to turn said third and fourth controllable switches ON during a maximum magnitude of a first polarity of a pulse of the chopped alternating current signal.

14. The pulse width modulated direct current--direct current converter circuit of claim 13 in which said first, second, third, fourth, fifth and sixth controllable switches comprise metal oxide semiconductor field effect transistors.

15. The pulse width modulated direct current--direct current converter circuit of claim 13 in which the first control signal and the third control signal are generated from a first common control signal by means of a first delay element for the first control signal and a second delay element for the third control signal and the second control signal and the fourth control signal are generated from a second common control signal by means of a third delay element for the second control signal and a fourth delay element for the third control signal.

16. The pulse width modulated direct current--direct current converter circuit of claim 15 in which the fifth control signal is generated by said second delay element and the sixth control signal is generated by the fourth delay element.

17. The pulse width modulated direct current--direct current converter circuit of claim 13 in which the first control signal and the third control signal are generated from a first common control signal by means of a first AND circuit receiving the first common control signal and a second common control signal, a first delay element for the first control signal receiving an output from said first AND circuit and a second delay element receiving the first common control signal for the third control signal, the second control signal and the fourth control signal are generated from a third common control signal by means of a second AND circuit receiving the third common control signal and a fourth common control signal, a third delay element for the second control signal receiving an output from said second AND circuit and a fourth delay element receiving the third common control signal for the fourth control signal.

18. The pulse width modulated direct current--direct current converter circuit of claim 17 in which the fifth control signal is generated from the second common control signal by means of a fifth delay element and the sixth control signal is generated from the fourth common control signal by means of a sixth delay element.