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Process for self-alignment and planarization of semiconductor chips attached by solder die adhesive to multi-chip modules

  • US 5,352,629 A
  • Filed: 01/19/1993
  • Issued: 10/04/1994
  • Est. Priority Date: 01/19/1993
  • Status: Expired due to Term
First Claim
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1. A method for attaching at least one semiconductor chip, with an electrical conductor disposed on an underside of each of said at least one chip, to a substrate having a surface, to cause self-alignment and PLANARIZATION of said at least one chip, comprising:

  • providing on said substrate surface an inner layer of electrical conductor having solder wettability;

    providing on said inner layer an outer layer of electrical conductor having solder nonwettability and having at least one window therein exposing said inner layer, said at least one window having a length and width substantially equal to an associated length and width of said at least one chip;

    placing a solder preform on each respective one of said at least one window;

    placing a chip on each respective one of said solder preforms;

    placing said substrate into a structure capable of applying isostatic pressure;

    overlaying said substrate and said at least one chip with a dielectric film layer;

    applying pressure over said dielectric film layer; and

    subsequentlyheating said substrate above the melting point of said solder preforms to align each of said at least one chip within said at least one window, and substantially simultaneously to planarize said at least one chip with respect to said surface.

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