Process for self-alignment and planarization of semiconductor chips attached by solder die adhesive to multi-chip modules

• US 5,352,629 A
• Filed: 01/19/1993
• Issued: 10/04/1994
• Est. Priority Date: 01/19/1993
• Status: Expired due to Term

• Current Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Original Assignee: General Electric Company
• Inventors: Daum, Wolfgang, Hennessy, William A., Paik, Kyung W.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Graybill, David E.
• Application Number:
  US08/006,297
• Time in Patent Office: 623 Days
• Field of Search: 437/189, 437/212, 437/216, 437/222, 228/123, 228/180.2, 228/254, 29/834, 29/840, 257/783, 257/772, 257/779
• US Class Current: 228/123.1
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/75101 Chamber
• CPC Class Codes: H01L 2224/75315 Elastomer inlay
• CPC Class Codes: H01L 2224/75317 Removable auxiliary member
• CPC Class Codes: H01L 2224/7598 specially adapted for batch processes
• CPC Class Codes: H01L 2224/83101 as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83205 Ultrasonic bonding
• CPC Class Codes: H01L 2224/83209 applying isostatic pressure, e.g. degassing using vacuum or a pressurised liquid
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/75 Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/0133 : Ternary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15157 : Top view
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides

Abstract

A method for attaching a chip to a substrate includes providing the substrate with an outer layer of an electrical conductor which is not wettable by solder and which has a window exposing an inner layer of electrical conductor that is wettable by solder. A solder preform is placed on the window exposing the inner layer, and the chip is placed on the solder preform. The substrate is then heated so as to melt the solder preform. To achieve planarity, the substrate is be positioned in a pressurizing chamber with a film overlay having higher pressure above the film overlay than underneath the overlay, and heated above the melting point of the solder.

Claims

1. A method for attaching at least one semiconductor chip, with an electrical conductor disposed on an underside of each of said at least one chip, to a substrate having a surface, to cause self-alignment and PLANARIZATION of said at least one chip, comprising:

providing on said substrate surface an inner layer of electrical conductor having solder wettability;

providing on said inner layer an outer layer of electrical conductor having solder nonwettability and having at least one window therein exposing said inner layer, said at least one window having a length and width substantially equal to an associated length and width of said at least one chip;

placing a solder preform on each respective one of said at least one window;

placing a chip on each respective one of said solder preforms;

placing said substrate into a structure capable of applying isostatic pressure;

overlaying said substrate and said at least one chip with a dielectric film layer;

applying pressure over said dielectric film layer; and

subsequently

heating said substrate above the melting point of said solder preforms to align each of said at least one chip within said at least one window, and substantially simultaneously to planarize said at least one chip with respect to said surface.

2. The method of claim 1, further including the step of providing chip wells in said substrate prior to providing said substrate with said outer layer and said inner layer.

3. The method of claim 2, wherein the step of providing chip wells comprises providing chip wells with slanted sidewalls.

4. The method of claim 2, further including the step of applying a vacuum under said dielectric film layer during the step of applying pressure over said dielectric film layer.

5. The method of claim 4, wherein said dielectric film layer comprises a polyimide.

6. The method of claim 4, further including the step of cooling said substrate while still applying said vacuum after the step of heating said substrate.

7. The method of claim 4, further including the steps of cooling said substrate after the step of heating said substrate, and thereafter removing said dielectric layer.

8. A method for attaching at least one semiconductor chip, each with an electrical conductor disposed on an underside thereof, to a substrate having a surface, and having chip wells therein, causing chip attachment, chip alignment, and chip planarization substantially simultaneously, comprising:

providing on said substrate surface an inner layer of electrical conductor having solder wettability;

providing on said inner layer an outer layer of an electrical conductor having solder nonwettability and having at least one window therein exposing said inner layer, said at least one window having a length and width substantially equal to an associated length and width of said at least one chip;

placing a solder preform on each respective one of said at least one window;

placing a chip on each respective one of said solder preforms;

placing said substrate into a structure capable of applying isostatic pressure;

overlaying said substrate and said at least one chip with a dielectric film layer;

applying pressure over said dielectric film layer; and

subsequently

heating said substrate above the melting point of said solder preforms to cause each of said at least one chip to be substantially simultaneously self-aligned within said at least one window and planarized with respect to said surface.

9. The method of claim 8, wherein

the step of providing said outer layer having windows exposing said inner layer is performed so that each respective window has a length and width substantially equal to the length and width of a predetermined respective one of said chips;

and

the step of placing a solder preform on each respective one of said windows is performed so that each respective solder preform has a length and width substantially equal to the length and width of the respective window on which it is situated.

10. The method of claim 9, further including the step of applying a vacuum under said dielectric film layer during the step of applying pressure over said dielectric film layer.

11. The method of claim 10, wherein said chip wells have slanted sidewalls.

12. The method of claim 8, further including the steps of:

applying a first solder flux on said inner layer through said windows prior to placing said preforms in said windows; and

applying a second solder flux on said solder preforms prior to placing said chips on said solder preforms.