Multichip packaged semiconductor device and method for manufacturing the same

• US 5,352,632 A
• Filed: 05/17/1993
• Issued: 10/04/1994
• Est. Priority Date: 02/08/1991
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sawaya, Hiromichi
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Picardat, Kevin M.
• Application Number:
  US08/062,013
• Time in Patent Office: 505 Days
• Field of Search: 437/209, 437/211, 437/212, 437/214, 437/215, 437/217, 437/220
• US Class Current: 29/827
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49524 the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/86 using tape automated bonding [TAB]
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: Y10T 29/49121 : Beam lead frame or beam lead device

Abstract

A plurality of semiconductor chips are mounted on a plurality of islands formed on a lead frame. Inner lead portions of the lead frame and electrode pads formed on the semiconductor chips are electrically connected to one another via first lead portions formed on a flexible resin tape and the electrode pads formed on the semiconductor chips are connected to one another via second lead portions formed on the flexible resin tape. The flexible resin tape on which the islands and inner lead portions of the lead frame, the plurality of semiconductor chips and the first and second lead portions are formed is sealed into a resin package.

Claims

1. A semiconductor device manufacturing method comprising:

a first step of mounting a plurality of semiconductor chips on at least one island formed on a lead frame;

a second step of disposing a flexible resin tape on said lead frame, said resin tape having a plurality of device holes formed in positions corresponding to mounting positions of said semiconductor chips and also having a wiring pattern for electrically connecting an inner lead portion of the lead frame to electrode pads of the semiconductor chips;

a third step of connecting one end of said wiring pattern formed on said flexible resin tape to the electrode pads formed on said plurality of semiconductor chips; and

a fourth step of connecting the another of said wiring pattern formed on said flexible resin tape to an inner lead section of said lead frame.

2. A semiconductor device manufacturing method according to claim 1, wherein said third step if effected by use of bump electrodes formed on said electrode pads.

3. A semiconductor device manufacturing method according to claim 1, wherein said fourth step is effected by use of alloy bonding.

4. A semiconductor device manufacturing method according to claim 1, wherein said wiring pattern is formed on the surface of said flexible resin tape such that the one end portion of the wiring pattern projects outside of said flexible resin tape with the other end portion projecting into said device holes.

5. A semiconductor device manufacturing method comprising:

a first step of mounting a plurality of semiconductor chips on at least one island formed on a lead frame;

a second step of disposing a flexible resin tape on said lead frame, said resin tape having a plurality of device holes formed in positions corresponding to mounting positions of said semiconductor chips, having a first wiring pattern for electrically connecting an inner lead portion of the lead frame to electrode pads of the semiconductor chips, and also having a second wiring pattern for interconnection of the electrode pads of said plurality of semiconductor chips;

a third step of connecting one end of said first wiring pattern formed on said flexible resin tape to the electrode pads formed on said plurality of semiconductor chips;

a fourth step of connecting said second wiring pattern formed on said flexible resin tape to the electrode pads formed on said plurality of semiconductor chips so as to electrically connect said semiconductor chips to one another; and

a fifth step of connecting another end of said first wiring pattern formed on said flexible resin tape to an inner lead section of said lead frame.

6. A semiconductor device manufacturing method according to claim 5, wherein said third and fourth steps are effected by use of bump electrodes formed on said electrode pads.

7. A semiconductor device manufacturing method according to claim 5, wherein said fifth step is effected by use of alloy bonding.

8. A semiconductor device manufacturing method according to claim 5, wherein said first wiring pattern is formed on the surface of said flexible resin tape such that the one end portion of the wiring pattern projects outside of said flexible resin tape with the other end portion projecting into said device hole, and said second wiring pattern is formed on the surface of said flexible resin tape such that one end portion of the second wiring pattern projects into said device holes, with another end portion of the second wiring pattern projecting outside of said flexible resin tape.