Flip chip package and method of making

• US 5,352,926 A
• Filed: 01/04/1993
• Issued: 10/04/1994
• Est. Priority Date: 01/04/1993
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Andrews, James A.
• Primary Examiner(s): Mintel, William
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US08/000,080
• Time in Patent Office: 638 Days
• Field of Search: 257/737, 257/747, 257/720, 257/778, 257/717, 257/778, 257/734, 437/195, 437/209, 437/215
• US Class Current: 257/717
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/0103 Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/10329 Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/13063 Metal-Semiconductor Field-Effect Transistor [MESFET]
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10T 29/49144 : by metal fusion

Abstract

A portion of a semiconductor die is rigidly flip chip bonded to a conductive base plate and portion is bonded to a flexible dielectric material to take advantage of the benefits of flip chip packaging while at the same time allowing for heat to be dissipated and for differential thermal expansion to be relieved. A semiconductor die having at least a first and a second bump formed thereon is rigidly connected to the base plate through the first bump and is flexibly connected to the base plate through the second bump.

Claims

1. A semiconductor package, comprising:

a base plate comprised of a thermally and electrically conductive material; and

a semiconductor die having at least a first and a second bump formed thereon, wherein the semiconductor die is rigidly connected to the base plate through the first bump and is flexibly connected to the base plate through the second bump by way of a flexible dielectric material which is disposed on a portion of the base plate.

2. The semiconductor package of claim 1 wherein an air gap is formed between at least a portion of the flexible dielectric material and the base plate.

3. The semiconductor package of claim 1, wherein the base plate is comprised of copper.

4. The semiconductor package of claim 1, wherein the first bump is electrically connected to a source of the semiconductor die.

5. The semiconductor package of claim 1, wherein the first bump is electrically connected to a heat dissipating area of the semiconductor die.

6. A semiconductor package, comprising:

a base plate comprised of a thermally and electrically conductive material;

a flexible material having a first surface and a second surface attached to the base plate at least a first conductive layer disposed on a portion of the second surface of the flexible material and in between portions of the flexible material;

a third and a fourth conductive layer disposed on a portion of the first surface of the flexible material, wherein the third and the fourth conductive layers are separated from each other and the third conductive layer is electrically connected to the first conductive layer; and

a semiconductor die having at least a first and a second bump formed thereon, wherein the first bump is disposed on the third conductive layer over at least a portion of the first conductive layer, and the second bump is disposed on the fourth conductive layer which is over the flexible material.

7. The semiconductor package of claim 6, further comprising a conductive slug disposed between the first conductive layer and the base plate, and an insulating material formed between two fifth conductive layers disposed between the fourth conductive layer and the base plate.

8. The semiconductor package of claim 6, wherein the base plate is comprised of copper.

9. The semiconductor package of claim 6, wherein the first, second, third, and fourth conductive layers are comprised of copper.

10. The semiconductor package of claim 6, wherein the first and the second bump are comprised of gold.

11. The semiconductor package of claim 6, wherein the first bump is electrically connected to a source of the semiconductor die.

12. The semiconductor package of claim 6, wherein the first bump is electrically connected to a heat dissipating area of the semiconductor die.

13. The semiconductor package of claim 6 wherein an air gap is formed between at least a portion of the flexible material and the base plate.

14. A method of fabricating a semiconductor package, comprising the steps of:

providing a base plate comprised of a thermally and electrically conductive material;

providing a semiconductor die having at least a first and a second bump formed thereon;

rigidly connecting the semiconductor die to the base plate through the first bump; and

flexibly connecting the semiconductor die to the base plate through the second bump by way of a flexible dielectric material which is disposed on a portion of the base plate.

15. The method of claim 14 wherein the step of flexibly connecting the semiconductor die to the base plate further comprises forming an air gap between at least a portion of the flexible dielectric material and the base plate.

16. The method of claim 14 wherein the step of providing a base plate further comprises providing a base plate comprised of copper.

17. The method of claim 14 further comprising the step of electrically connecting the first bump to a source of the semiconductor die.

18. The method of claim 14 further comprising the step of electrically connecting the first bump to a heat dissipating area of the semiconductor die.

19. A semiconductor package, comprising:

a base plate comprised of a thermally and electrically conductive material; and

a semiconductor die having at least a first and a second bump formed thereon, wherein the semiconductor die is rigidly connected to the base plate through the first bump and wherein the first bump is electrically connected to a heat dissipating area of the semiconductor die and further wherein the semiconductor die is flexibly connected to the base plate through the second bump.