Amplifier circuit

• US 5,352,992 A
• Filed: 05/07/1993
• Issued: 10/04/1994
• Est. Priority Date: 05/07/1992
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Asazawa, Hiroshi
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): Abraham, Fetsum
• Application Number:
  US08/059,061
• Time in Patent Office: 515 Days
• Field of Search: 330/291, 330/293, 330/296, 330/310, 330/311
• US Class Current: 330/310
• CPC Class Codes: H03F 3/3088 with asymmetric control, i.e. one control branch containing a supplementary phase inverting transistor

Abstract

An amplifier circuit having an emitter-grounded amplifying stage formed of a transistor Q1 and a load resistor R_L and having an output stage including an emitter follower formed of transistors Q2 and Q3. The base of the transistor Q1 of the amplifying stage and the base of the transistor Q3 of the output stage are connected with each other for receiving input signals and biased by a bias circuitry 5. The input signals thus given to the base of transistor Q3 for the emitter follower of the output stage cause the transistors Q2 and Q3 to alternately turn on and off to provide a higher output driving power to the load connected to the output terminal than prior art amplifier circuits having conventional emitter followers and resistor feedback amplification networks.

Claims

1. An amplifier circuit, comprising:

an amplifying stage including a first emitter-grounded bipolar transistor and a load circuitry; and

an output stage including

a second bipolar transistor serving as an emitter-follower having its base connected with the output of said amplifying stage; and

a third bipolar transistor having its base connected with the base of said first bipolar transistor, for driving said emitter-follower, output of said amplifier circuit being taken between the emitter of said second bipolar transistor and the collector of said third bipolar transistor.

2. An amplifier circuit, comprising:

an emitter-grounded amplifying stage including a first emitter-grounded bipolar transistor;

a load circuitry connected between the collector of said first bipolar transistor and a power source terminal; and

a bias circuitry for supplying power to the base of said first bipolar transistor,

the base and collector of said first bipolar transistor serving as an input and output ends, respectively, of said emitter-grounded amplifying stage, and

an emitter follower including

a second bipolar transistor having its collector connected with said power source terminal and its base connected with the output of said emitter-grounded amplifying stage;

a third bipolar transistor having its collector connected with the emitter of said second bipolar transistor and its emitter grounded,

a junction connecting the emitter of said second bipolar transistor and the collector of said third bipolar transistor, serving as a output terminal of said amplifier circuit,

the base of said third bipolar transistor connected with the base of said first bipolar transistor.

3. The amplifier circuit as claimed in claim 2, wherein said bias circuitry comprises a resistance feedback circuitry connected between the base and the collector of said first bipolar transistor.

4. The amplifier circuit as claimed in claim 2, wherein said bias circuitry comprises a resistance feedback circuit connected between the base of said first bipolar transistor and the emitter of said second bipolar transistor.

5. The amplifier circuit as claimed in claim 2, wherein the base of said third bipolar transistor is connected with the base of said first bipolar transistor via a resistor.