EEPROM-backed FIFO memory

• US 5,353,248 A
• Filed: 04/14/1992
• Issued: 10/04/1994
• Est. Priority Date: 04/14/1992
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Gupta, Anil
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): DINH, SON T
• Application Number:
  US07/868,174
• Time in Patent Office: 903 Days
• Field of Search: 365/228, 365/154, 365/221
• US Class Current: 365/154
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down

Abstract

A first-in, first-out (FIFO) static random access memory (SRAM) device includes EEPROM cells which provide non-volatile backup capability. The sizing of each SRAM cell is such that its associated EEPROM cell is automatically programmed via the output of the SRAM cell. Upon power-up, the EEPROM cell restores the SRAM cell to the inverse of whatever state it was in prior to the most recent EEPROM programming (before a preceding power-down). This provides non-volatility to the SRAM without a significant increase in manufacturing costs or overhead.

Claims

1. A static random access memory cell for storing a momentarily applied binary digit and for automatically returning to a state indicative of said applied binary digit after any interruption in the power supplied to said cell comprising:

a first relatively strong inverter having an input terminal and an output terminal, said binary digit being momentarily applied to said input terminal;

a second relatively weak inverter having an input terminal connected to the output terminal of said first inverter and an output terminal connected to the input terminal of said first inverter, said second inverter being weak enough to allow said momentarily applied binary digit to control the state of said first inverter, but strong enough to hold said first inverter in the state established by said momentarily applied binary digit even after said binary digit is no longer being applied;

a first controllable potential source;

a second controllable potential source;

an electrically erasable programmable read-only memory (EEPROM) transistor having a gate, a floating gate, a source, and a drain, said gate being connected to said first controllable potential source, said EEPROM transistor being connected between said output terminal of said first inverter and said second controllable potential source via said source and drain, said EEPROM transistor being at least initially non-conducting as a result of a charge stored on said floating gate of said EEPROM transistor; and

means for momentarily increasing the potential of the output terminal of said first inverter if and only if said momentarily applied binary digit has placed said first inverter in a predetermined state, said increased potential being sufficient to remove said charge from said EEPROM transistor and thereby rendering said EEPROM transistor conducting so that if the power supplied to said cell is interrupted, said EEPROM transistor causes said first inverter to return to a first state when said power is restored if said EEPROM transistor is non-conducting, and causes said first inverter to return to a second state when said power is restored if said EEPROM transistor is conducting;

wherein

said first controllable potential source momentarily applies a relatively very high potential to said gate to cause said charge to be stored on said floating gate during a global erase of said EEPROM; and

said first controllable potential source applies a relatively low potential to said gate while said means for momentarily increasing is operating to increase the potential of the output of said first inverter.

2. The apparatus defined in claim 1 wherein said first controllable potential source applies said relatively low potential and said second controllable potential source applies said relatively low potential and said means for momentarily increasing applies a potential intermediate said relatively high potential and said relatively low potential while said EEPROM transistor is causing said first inverter to return to said first or said second state when said power is restored.

3. The apparatus defined in claim 1 wherein said cell is one of a series of similar cells, and wherein said apparatus further comprises:

a plurality of pass transistors, each of which is associated with a respective one of said cells, each pass transistor being connected in series between the output terminal of the first inverter in the associated cell and the input terminal of the first inverter of the next cell in said series and each pass transistor being operable such that a plurality of pass transistors may be enabled at the same time so that a binary digit may be passed to a plurality of cells essentially simultaneously.

4. The method of operating a static random access memory cell which includes (1) means for storing a momentarily applied binary digit, (2) an electrically erasable programmable read-only memory (EEPROM) transistor for restoring said means for storing to a state indicative of said applied binary digit after any interruption in the power supply to said cell, said EEPROM transistor having a gate, a floating gate, and a source-drain channel, said source-drain channel connected to an output terminal of said means for storing, and (3) a controllable potential source connected to said gate, said method comprising the steps of:

clearing said EEPROM transistor by storing a charge on said floating gate to render said EEPROM transistor non-conducting;

momentarily applying said binary digit to said means for storing to place said means for storing in a state indicative of said applied binary digit;

raising the potential of the output terminal of said means for storing to a potential greater than the normal logic potential if and only if said means for storing is in a predetermined one of said first and second states in order to remove said charge from said floating gate so that the presence or absence of charge on said EEPROM transistor is indicative of the state of said means for storing;

applying a relatively low potential to said gate of said EEPROM transistor while performing said raising step; and

using said EEPROM transistor to control the state of said means for storing after any interruption in the power supplied to said cell, said EEPROM transistor placing said means for storing in a first state after a power interruption if a charge is present on said EEPROM transistor, and said EEPROM transistor placing said means for storing in a second state after a power interruption if a charge is absent from said EEPROM transistor.

5. The method defined in claim 4 wherein said EEPROM transistor has a gate, a floating gate, and a source-drain channel, wherein said source-drain channel is connected to an output terminal of said means for storing, wherein said charge is stored on said floating gate and, if present, renders said source-drain channel non-conducting regardless of the normal logic level applied to said gate, and wherein said step of using said EEPROM transistor comprises the step of:

applying to said gate a potential sufficient to cause said source-drain channel to conduct if and only if no charge is present on said floating gate, thereby placing said means for storing in said second state.

6. The method defined in claim 5 wherein said step of using said EEPROM transistor further comprises the step of:

applying a potential to said output terminal which is sufficient to place said means for storing in said first state unless said source-drain channel is conducting.

7. The method defined in claim 4 wherein said EEPROM transistor has a gate, a floating gate, and a source-drain channel, wherein said source-drain channel is connected to an output terminal of said means for storing, wherein said charge is stored on said floating gate, wherein said source-drain channel can be made to conduct by applying a predetermined potential to said gate only in the absence of a charge on said floating gate, and wherein said method further comprises the step of:

applying to said gate a potential which is not sufficient to cause said source-drain channel to conduct at all times, after performing said step of storing a charge on said EEPROM transistor, except during performance of said step of using said EEPROM transistor to control the state of said means for storing after any interruption in the power supplied to said cell.

8. The method defined in claim 4 wherein said cell is one of a plurality of similar cells connected in a series such that an output terminal of the means for storing in each cell is connected to an input terminal of the means for storing in the next cell in the series via a pass transistor, and wherein said step of momentarily applying said binary digit comprises the steps of:

enabling all of said pass transistors;

momentarily applying a binary digit to the input terminal of said first cell so that said binary digit passes through all of said cells to the cell which is most remote from said first cell;

disabling the pass transistor which is immediately upstream from said most remote cell;

momentarily applying another binary digit to the input terminal of said first cell so that said another binary digit passes through all of said cells to the cell which is just upstream from the most recently disabled pass transistor;

disabling the pass transistor which is just upstream from the most recently disabled pass transistor; and

repeating the last two steps until binary digits have been stored in all of said cells and all of said pass transistors have been disabled.

9. Apparatus to provide a non-volatile first-in first-out (FIFO) memory device comprising:

input and output terminals;

an input n-channel transistor having a gate and two sides, with one side being connected to said input terminal;

a plurality of pass transistors;

a plurality of non-volatily backed-up static random access memory (SRAM) cells connected in series, each cell having an input and an output, where said input of said first SRAM cell is connected to said other side of said input transistor and said output of said last SRAM cell is connected to said output terminal, and where one of said plurality of said pass transistors is connected between each pair of SRAM cells within said series connection, wherein a subset of said plurality of said pass transistors can be enabled simultaneously so that a binary digit may be passed to a plurality of SRAM cells essentially simultaneously; and

a global predetermined voltage source which provides power to each of said SRAM cells;

wherein each of said plurality of non-volatily backed-up SRAM cells comprises;

a weak inverter comprising a first n-channel transistor having a gate and two sides; and

a first p-channel transistor having a gate and two sides, connected serially between said global predetermined voltage source and said one side of said first n-channel transistor, with said other side of said first n-channel transistor being connected to a logical 0;

a strong inverter comprising a second n-channel transistor having a gate and two sides, with said one side connected to logical 0;

a second p-channel transistor having a gate and two sides; and

a bias p-channel transistor having a gate and two sides, connected serially between said global predetermined voltage source and said one side of said second p-channel transistor, with said other side of said second p-channel transistor being connected to said other side of said n-channel transistor;

an output n-channel transistor serially connected between said output of said non-volatily backed-up SRAM cell and said input of said next sequential non-volatily backed-up SRAM cell;

a power-on-reset transistor having a gate and two sides, with said one side being connected to logical 0;

an electrically erasable programmable read-only memory (EEPROM) cell having an output terminal;

a SRAM cell comprising said weak and strong inverters, having an input connected to said other side of said power-on-reset transistor, and an output which is connected to said output terminal of said EEPROM cell; and

means for programming said EEPROM cell.

10. The apparatus defined in claim 9 wherein said input of said SRAM cell is also connected to a node between said serial connection of said first n-channel transistor and said first p-channel transistor, and is also connected to a node between a connection of said gates of said second n-channel and said second p-channel transistors.

11. The apparatus defined in claim 10 wherein said output of said SRAM cell is connected to a node between said serial connection of said second n-channel transistor and said second p-channel transistor, and is also connected to a node between a connection of said gates of said first n-channel and said first p-channel transistors.

12. The apparatus defined in claim 11 wherein said EEPROM cell comprises:

a first predetermined voltage source;

a second predetermined voltage source; and

a floating gate transistor having a gate connected to said first predetermined voltage source, and one end connected to said second predetermined voltage source, said other end being connected to said output terminal of said EEPROM cell.

13. The apparatus defined in claim 12 wherein said means for programming said EEPROM cell comprises:

setting said first and second predetermined voltage sources to a logical 0; and

momentarily setting said global predetermined voltage source from a relatively high voltage to a relatively very high voltage.

14. The apparatus defined in claim 13 wherein said means for restoring information comprises:

setting said power-on-reset transistor to be conducting;

setting said bias p-channel transistor to a voltage about 3-3.5 volts;

setting said second predetermined voltage source to a logical 0;

setting said global predetermined voltage source from a power-off state to a relatively high voltage; and

pulsing said first predetermined voltage source to a relatively high voltage.

15. The apparatus defined in claim 13 wherein said relatively high voltage is about 5 volts.

16. The apparatus defined in claim 13 wherein said relatively very high voltage is about 15 volts.

17. The apparatus defined in claim 14 wherein said relatively high voltage is about 5 volts.