EEPROM-backed FIFO memory
First Claim
1. A static random access memory cell for storing a momentarily applied binary digit and for automatically returning to a state indicative of said applied binary digit after any interruption in the power supplied to said cell comprising:
- a first relatively strong inverter having an input terminal and an output terminal, said binary digit being momentarily applied to said input terminal;
a second relatively weak inverter having an input terminal connected to the output terminal of said first inverter and an output terminal connected to the input terminal of said first inverter, said second inverter being weak enough to allow said momentarily applied binary digit to control the state of said first inverter, but strong enough to hold said first inverter in the state established by said momentarily applied binary digit even after said binary digit is no longer being applied;
a first controllable potential source;
a second controllable potential source;
an electrically erasable programmable read-only memory (EEPROM) transistor having a gate, a floating gate, a source, and a drain, said gate being connected to said first controllable potential source, said EEPROM transistor being connected between said output terminal of said first inverter and said second controllable potential source via said source and drain, said EEPROM transistor being at least initially non-conducting as a result of a charge stored on said floating gate of said EEPROM transistor; and
means for momentarily increasing the potential of the output terminal of said first inverter if and only if said momentarily applied binary digit has placed said first inverter in a predetermined state, said increased potential being sufficient to remove said charge from said EEPROM transistor and thereby rendering said EEPROM transistor conducting so that if the power supplied to said cell is interrupted, said EEPROM transistor causes said first inverter to return to a first state when said power is restored if said EEPROM transistor is non-conducting, and causes said first inverter to return to a second state when said power is restored if said EEPROM transistor is conducting;
whereinsaid first controllable potential source momentarily applies a relatively very high potential to said gate to cause said charge to be stored on said floating gate during a global erase of said EEPROM; and
said first controllable potential source applies a relatively low potential to said gate while said means for momentarily increasing is operating to increase the potential of the output of said first inverter.
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Accused Products
Abstract
A first-in, first-out (FIFO) static random access memory (SRAM) device includes EEPROM cells which provide non-volatile backup capability. The sizing of each SRAM cell is such that its associated EEPROM cell is automatically programmed via the output of the SRAM cell. Upon power-up, the EEPROM cell restores the SRAM cell to the inverse of whatever state it was in prior to the most recent EEPROM programming (before a preceding power-down). This provides non-volatility to the SRAM without a significant increase in manufacturing costs or overhead.
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Citations
17 Claims
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1. A static random access memory cell for storing a momentarily applied binary digit and for automatically returning to a state indicative of said applied binary digit after any interruption in the power supplied to said cell comprising:
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a first relatively strong inverter having an input terminal and an output terminal, said binary digit being momentarily applied to said input terminal; a second relatively weak inverter having an input terminal connected to the output terminal of said first inverter and an output terminal connected to the input terminal of said first inverter, said second inverter being weak enough to allow said momentarily applied binary digit to control the state of said first inverter, but strong enough to hold said first inverter in the state established by said momentarily applied binary digit even after said binary digit is no longer being applied; a first controllable potential source; a second controllable potential source; an electrically erasable programmable read-only memory (EEPROM) transistor having a gate, a floating gate, a source, and a drain, said gate being connected to said first controllable potential source, said EEPROM transistor being connected between said output terminal of said first inverter and said second controllable potential source via said source and drain, said EEPROM transistor being at least initially non-conducting as a result of a charge stored on said floating gate of said EEPROM transistor; and means for momentarily increasing the potential of the output terminal of said first inverter if and only if said momentarily applied binary digit has placed said first inverter in a predetermined state, said increased potential being sufficient to remove said charge from said EEPROM transistor and thereby rendering said EEPROM transistor conducting so that if the power supplied to said cell is interrupted, said EEPROM transistor causes said first inverter to return to a first state when said power is restored if said EEPROM transistor is non-conducting, and causes said first inverter to return to a second state when said power is restored if said EEPROM transistor is conducting;
whereinsaid first controllable potential source momentarily applies a relatively very high potential to said gate to cause said charge to be stored on said floating gate during a global erase of said EEPROM; and said first controllable potential source applies a relatively low potential to said gate while said means for momentarily increasing is operating to increase the potential of the output of said first inverter. - View Dependent Claims (2, 3)
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4. The method of operating a static random access memory cell which includes (1) means for storing a momentarily applied binary digit, (2) an electrically erasable programmable read-only memory (EEPROM) transistor for restoring said means for storing to a state indicative of said applied binary digit after any interruption in the power supply to said cell, said EEPROM transistor having a gate, a floating gate, and a source-drain channel, said source-drain channel connected to an output terminal of said means for storing, and (3) a controllable potential source connected to said gate, said method comprising the steps of:
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clearing said EEPROM transistor by storing a charge on said floating gate to render said EEPROM transistor non-conducting; momentarily applying said binary digit to said means for storing to place said means for storing in a state indicative of said applied binary digit; raising the potential of the output terminal of said means for storing to a potential greater than the normal logic potential if and only if said means for storing is in a predetermined one of said first and second states in order to remove said charge from said floating gate so that the presence or absence of charge on said EEPROM transistor is indicative of the state of said means for storing; applying a relatively low potential to said gate of said EEPROM transistor while performing said raising step; and using said EEPROM transistor to control the state of said means for storing after any interruption in the power supplied to said cell, said EEPROM transistor placing said means for storing in a first state after a power interruption if a charge is present on said EEPROM transistor, and said EEPROM transistor placing said means for storing in a second state after a power interruption if a charge is absent from said EEPROM transistor. - View Dependent Claims (5, 6, 7, 8)
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9. Apparatus to provide a non-volatile first-in first-out (FIFO) memory device comprising:
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input and output terminals; an input n-channel transistor having a gate and two sides, with one side being connected to said input terminal; a plurality of pass transistors; a plurality of non-volatily backed-up static random access memory (SRAM) cells connected in series, each cell having an input and an output, where said input of said first SRAM cell is connected to said other side of said input transistor and said output of said last SRAM cell is connected to said output terminal, and where one of said plurality of said pass transistors is connected between each pair of SRAM cells within said series connection, wherein a subset of said plurality of said pass transistors can be enabled simultaneously so that a binary digit may be passed to a plurality of SRAM cells essentially simultaneously; and a global predetermined voltage source which provides power to each of said SRAM cells; wherein each of said plurality of non-volatily backed-up SRAM cells comprises; a weak inverter comprising a first n-channel transistor having a gate and two sides; and
a first p-channel transistor having a gate and two sides, connected serially between said global predetermined voltage source and said one side of said first n-channel transistor, with said other side of said first n-channel transistor being connected to a logical 0;a strong inverter comprising a second n-channel transistor having a gate and two sides, with said one side connected to logical 0;
a second p-channel transistor having a gate and two sides; and
a bias p-channel transistor having a gate and two sides, connected serially between said global predetermined voltage source and said one side of said second p-channel transistor, with said other side of said second p-channel transistor being connected to said other side of said n-channel transistor;an output n-channel transistor serially connected between said output of said non-volatily backed-up SRAM cell and said input of said next sequential non-volatily backed-up SRAM cell; a power-on-reset transistor having a gate and two sides, with said one side being connected to logical 0; an electrically erasable programmable read-only memory (EEPROM) cell having an output terminal; a SRAM cell comprising said weak and strong inverters, having an input connected to said other side of said power-on-reset transistor, and an output which is connected to said output terminal of said EEPROM cell; and means for programming said EEPROM cell. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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Specification