Semiconductor memory device having burn-in test circuit

• US 5,353,254 A
• Filed: 05/21/1992
• Issued: 10/04/1994
• Est. Priority Date: 05/21/1992
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sakamoto, Harumi
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): NIRANJAN, FRANK
• Application Number:
  US07/887,442
• Time in Patent Office: 866 Days
• Field of Search: 324/158 R, 371/15.1, 371/21.1, 371/25.1, 439/68, 439/70, 439/43, 439/46, 439/49, 439/54, 365/201
• US Class Current: 365/201
• CPC Class Codes: G06F 11/2733 Test interface between tester and unit under test
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

The described embodiments of the disclosed invention provide a semiconductor devices, test apparatus for the semiconductor devices and a method for testing the semiconductor devices. The semiconductor devices may have many different types of pin counts and configurations. Each semiconductor device includes standardized test circuitry. The necessary pins to operate the test circuitry are included in a standardized position on the semiconductor devices relative to the positioning of the semiconductor devices in the test apparatus. Thus a single test apparatus may be utilized to test semiconductor devices having a wide range of pin configurations.

Claims

1. A system for testing a plurality of types of packaged integrated circuits having a plurality of pin configurations comprising:

a socket capable of receiving said plurality of pin configurations;

a reference voltage terminal provided at a first physical pin location of said socket, each of said integrated circuits having a pin for receiving said reference voltage at said first physical pin location;

a supply voltage terminal provided at a second physical pin location of said socket, each of said integrated circuits having a pin for receiving said supply voltage at said second physical pin location; and

at least one control signal terminal provided at a third physical pin location of said socket, each of said integrated circuits including a test circuit for receiving said control signal source and generating control signals appropriate for that integrated circuit, and each integrated circuit having a pin for receiving said control signal at said third physical location.

2. The system of claim 1 wherein said supply voltage provided on said supply voltage terminal is greater than a normal supply level for periods of time determined to coordinate temporally with said control signal.

3. The system of claim 1 wherein said system performs a burn-in test.

4. The system of claim 1 wherein said integrated circuits are memory circuits.

5. The system of claim 1 wherein said integrated circuits are programmable gate arrays.

6. The system of claim 1 further comprising means of elevating the temperature of the integrated circuit being tested.

7. The system of claim 6 wherein said means of elevating the temperature of the integrated circuit is capable of raising the temperature of the integrated circuit to at least 125°

C.

8. The system of claim 1 wherein said pin configurations include 70 and 36 pin dual in-line packages.

9. The system of claim 1 wherein said at least one control signal comprises a first, second and third control signals provided at said third, a fourth and a fifth pin position, respectively.

10. A method of testing a plurality of types of packaged integrated circuits having a plurality of pin configurations in a single testing system, comprising the steps of:

providing a socket capable of receiving said plurality of pin configurations;

providing a reference voltage terminal at a first physical pin location of said socket, each of said integrated circuits having a pin for receiving said reference voltage at said first physical pin location;

providing a supply voltage terminal at a second physical pin location of said socket, each of said integrated circuits having a pin for receiving said supply voltage at said second physical pin location; and

providing at least one control signal terminal at a third physical pin location of said socket, each of said integrated circuits including a test circuit for receiving said control signal source and generating control signals appropriate for that integrated circuit, and each integrated circuit having a pin for receiving said control signal at said third physical location.

11. The method of claim 10 wherein said supply voltage provided on said supply voltage terminal is provided at a level greater than a normal supply level for periods of time determined to coordinate temporally with said control signal.

12. The method of claim 10 wherein said method is used to perform a burn-in test.

13. The method of claim 10 wherein said integrated circuits are memory circuits.

14. The method of claim 10 wherein said integrated circuits are programmable gate arrays.

15. The method of claim 10 further comprising the step of elevating the temperature of the integrated circuit being tested.

16. The system of claim 15 wherein said step of elevating the temperature of the integrated circuit raises the temperature of the integrated circuit to at least 125°

C.

17. The system of claim 10 wherein said pin configurations include 70 and 36 pin dual in-line packages.

18. The system of claim 10 wherein said at least one control signal comprises a first, second and third control signals provided at said third, a fourth and a fifth pin position, respectively.