Semiconductor memory device having burn-in test circuit
First Claim
1. A system for testing a plurality of types of packaged integrated circuits having a plurality of pin configurations comprising:
- a socket capable of receiving said plurality of pin configurations;
a reference voltage terminal provided at a first physical pin location of said socket, each of said integrated circuits having a pin for receiving said reference voltage at said first physical pin location;
a supply voltage terminal provided at a second physical pin location of said socket, each of said integrated circuits having a pin for receiving said supply voltage at said second physical pin location; and
at least one control signal terminal provided at a third physical pin location of said socket, each of said integrated circuits including a test circuit for receiving said control signal source and generating control signals appropriate for that integrated circuit, and each integrated circuit having a pin for receiving said control signal at said third physical location.
1 Assignment
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Accused Products
Abstract
The described embodiments of the disclosed invention provide a semiconductor devices, test apparatus for the semiconductor devices and a method for testing the semiconductor devices. The semiconductor devices may have many different types of pin counts and configurations. Each semiconductor device includes standardized test circuitry. The necessary pins to operate the test circuitry are included in a standardized position on the semiconductor devices relative to the positioning of the semiconductor devices in the test apparatus. Thus a single test apparatus may be utilized to test semiconductor devices having a wide range of pin configurations.
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Citations
18 Claims
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1. A system for testing a plurality of types of packaged integrated circuits having a plurality of pin configurations comprising:
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a socket capable of receiving said plurality of pin configurations; a reference voltage terminal provided at a first physical pin location of said socket, each of said integrated circuits having a pin for receiving said reference voltage at said first physical pin location; a supply voltage terminal provided at a second physical pin location of said socket, each of said integrated circuits having a pin for receiving said supply voltage at said second physical pin location; and at least one control signal terminal provided at a third physical pin location of said socket, each of said integrated circuits including a test circuit for receiving said control signal source and generating control signals appropriate for that integrated circuit, and each integrated circuit having a pin for receiving said control signal at said third physical location. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of testing a plurality of types of packaged integrated circuits having a plurality of pin configurations in a single testing system, comprising the steps of:
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providing a socket capable of receiving said plurality of pin configurations; providing a reference voltage terminal at a first physical pin location of said socket, each of said integrated circuits having a pin for receiving said reference voltage at said first physical pin location; providing a supply voltage terminal at a second physical pin location of said socket, each of said integrated circuits having a pin for receiving said supply voltage at said second physical pin location; and providing at least one control signal terminal at a third physical pin location of said socket, each of said integrated circuits including a test circuit for receiving said control signal source and generating control signals appropriate for that integrated circuit, and each integrated circuit having a pin for receiving said control signal at said third physical location. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification