Block specific status information in a memory device
First Claim
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1. A flash memory device, comprising:
- a plurality of flash array blocks, each flash array block comprising a plurality of flash cells;
block status register circuit comprising a plurality of block status registers, each block status register storing a block status for one of the flash array blocks;
flash array controller circuit performing program and erase operations on the flash array blocks, the flash array controller maintaining the block status in each block status register;
interface circuit enabling read access of the block status registers over a host bus.
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Abstract
A flash memory device having a plurality of flash array blocks and a block status register circuit containing a block status register for storing a block status for each flash array block. A flash array controller circuit in the flash memory device performs program or erase operations on the flash array blocks, and maintains the block status in each block status register. An interface circuit in the flash memory device enables read access of the block status registers over a bus.
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Citations
34 Claims
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1. A flash memory device, comprising:
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a plurality of flash array blocks, each flash array block comprising a plurality of flash cells; block status register circuit comprising a plurality of block status registers, each block status register storing a block status for one of the flash array blocks; flash array controller circuit performing program and erase operations on the flash array blocks, the flash array controller maintaining the block status in each block status register; interface circuit enabling read access of the block status registers over a host bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A computer system, comprising:
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flash memory device providing block specific status information for a flash cell array comprising a plurality of flash array blocks, the block specific status information accessible over a host bus; main memory means storing a set of write data for a write operation to the flash cell array; central processing means reading the block specific status information from the flash memory device, the central processing means reading the write data from the main memory means and transferring a write command and the write data over the host bus. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A computer system, comprising:
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circuit for providing block specific status information for a flash cell array comprising a plurality of flash array blocks, such that the block specific status information is accessible over a host bus; main memory means storing a set of write data for a write operation to the flash cell array; central processing means reading the block specific status information, the central processing means reading the write data from the main memory means and transferring a write command and the write data over the host bus. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34)
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Specification