Tap-weight controller for adaptive matched filter receiver

• US 5,353,306 A
• Filed: 12/28/1992
• Issued: 10/04/1994
• Est. Priority Date: 12/27/1991
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Yamamoto, Takeshi
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): TSE, YOUNG TOI
• Application Number:
  US07/997,183
• Time in Patent Office: 645 Days
• Field of Search: 375/11-12, 375/14, 375/96, 375/101, 375/103, 379/403, 379/411, 364/724.11, 364/724.16, 364/724.19, 364/724.2
• US Class Current: 375/233
• CPC Class Codes: H03H 21/0018 Matched filters
• CPC Class Codes: H04B 1/123 using adaptive balancing or compensation means adaptive filter circuits and algorithms H03H
• CPC Class Codes: H04B 7/005 Control of transmission; Equalising

Abstract

In an adaptive matched filter with a decision feedback equalizer (DFE), a tap-weight controller of the matched filter includes a tapped delay line having a series of delay elements for receiving an incoming digital signal to produce successively delayed signals at successive taps of the delay line so that the signal at the center tap coincides with an output of the DFE. Cross-correlators are associated respectively with tap-weight multipliers of the matched filter. In each cross-correlator, cross-correlation is detected between a digital sample from the DFE and a delayed version of the corresponding digital sample. An average value is taken of the cross-correlation to produce higher significant bits of a tap-weight coefficient for the corresponding tap-weight multiplier. The most significant bit of the output of the higher significant bits is inverted and a group of bits is produced, each having the same binary value as the inverted most significant bit. The group of bits is supplied to the corresponding tap-weight multiplier as lower significant bits of the tap-weight coefficient.

Claims

1. A receiver comprising:

an equalizer;

analog-to-digital (A/D) converter means for receiving signals at symbol rate and converting the signals into digital samples at a rate which is n times higher than the symbol rate, where n is an integer equal to or greater than 2;

a transversal filter having a first tapped delay line of a series of delay elements for receiving the digital samples from the A/D converter means, a plurality of tap-weight multipliers connected respectively to successive taps of the delay line, and means for summing outputs of the tap-weight multipliers to produce a matched filter output and supplying the matched filter output to said equalizer at the symbol rate;

a tap-weight controller having a second tapped delay line of a series of delay elements for receiving the digital samples from the A/D converter means so that a digital sample at a center tap of the second delay line is substantially time coincident with a digital sample from the equalizer, and a plurality of cross-correlators corresponding respectively to the tap-weight multipliers of said transversal filter, each of the cross-correlators being connected to a corresponding one of successive taps of the second delay line, each of the cross-correlators comprising;

latch means for receiving a digital sample from the corresponding tap of the second delay line and latching the digital sample at the symbol rate;

a multiplier for multiplying the latched digital sample with the digital sample from the equalizer to produce a digital sample of a correlation value;

averaging means for successively summing the digital sample from the multiplier to produce an output digital sample representing an average of a summed correlation values and supplying the output digital sample as higher significant bits of a tap-weight coefficient to a corresponding one of said tap-weight multipliers; and

inverter means for inverting a most significant bit of the output digital sample of the averaging means, producing a group of bits each having the same binary value as the inverted most significant bit, and supplying the group of bits to the corresponding tap-weight multiplier as lower significant bits of the tap-weight coefficient.

2. A receiver as claimed in claim 1, wherein said equalizer comprises a decision feedback equalizer clocked at the symbol rate.