Neural network circuit

• US 5,353,383 A
• Filed: 07/07/1992
• Issued: 10/04/1994
• Est. Priority Date: 07/09/1990
• Status: Expired due to Fees

• Current Assignee: Nippon Telegraph and Telephone Corporation
• Original Assignee: Nippon Telegraph and Telephone Corporation
• Inventors: Iwata, Atsushi, Saito, Osamu, Amemiya, Yoshihito, Uchimura, Kuniharu
• Primary Examiner(s): MacDonald, Allen R.
• Application Number:
  US07/909,993
• Time in Patent Office: 819 Days
• Field of Search: 395/24, 395/25, 395/27, 307/201, 364/807
• US Class Current: 706/27
• CPC Class Codes: G06F 18/2453 non-linear, e.g. polynomial classifier
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

A neural network circuit including a number n of weight coefficients (W1-Wn) corresponding to a number n of inputs, subtraction circuits for determining the difference between inputs and the weight coefficients in each input terminal, the result thereof being inputted into absolute value circuits, all calculation results of the absolute value circuits corresponding to the inputs and the weight coefficients being inputted into an addition circuit and accumulated, and this accumulation result determining the output value. A threshold value circuit determines the final output value, according to a step function pattern, a polygonal line pattern, or a sigmoid function pattern, depending on the object. In the case in which a neural network circuit is realized by means of digital circuits, the absolute value circuits can include simply EX-OR logic (exclusive OR) gates. Furthermore, in the case in which the input terminals have two input paths and two weight coefficients corresponding to each input path, the neuron circuits form a recognition area having a flexible shape which is controlled by the weight coefficients.

Claims

1. A neural network circuit including a plurality of neuron circuits, comprising:

a plurality n of input terminals for receiving input signals, where n is an integer greater than 1;

two weight coefficients corresponding to each of said input terminals;

a first subtraction circuit for calculating a first difference between a larger one of said two weight coefficients and a corresponding input signal;

a first rectification circuit for discriminating and passing only positive value results of said first subtraction circuit;

a first non-linear circuit producing a non-linear output according to results from said first rectification circuit;

a second subtraction circuit for calculating a second difference between a smaller one of said two weight coefficients and a corresponding input signal;

a second rectification circuit for discriminating and passing only positive value results of said second subtraction circuit;

a second non-linear circuit producing a non-linear output according to results from said second rectification circuit;

an addition circuit for adding and accumulating outputs of said first and second non-linear circuits for each of said plurality n of input terminals;

a threshold value circuit having a predetermined threshold value for determining a magnitude of a result of said accumulation in accordance with said predetermined threshold value, and outputting said accumulation result, wherein said neuron circuits use the output results of said threshold value circuit as output signals; and

means of connecting input and output terminals of said neuron circuits, said neuron circuits having independent said weight coefficients with respect to a plurality of said input signals inputted into each of said network circuits for executing calculations, an output value of at least one of said neuron circuits being an output signal of said network circuit, and said two weight coefficients and a size of said threshold value of said threshold value circuit controlling said network circuit.

2. A neural network circuit according to claim 1, further comprising control means provided in said addition circuit for determining whether to truncate remaining addition calculations, said control means comparing a size relationship of an intermediate result of an accumulation addition corresponding to each input signal and said threshold value of said threshold value circuit, said threshold value circuit determining said output signal according to the comparison.

3. A neural network circuit in accordance with claim 1, wherein

said addition circuit has m output terminals, where m is an integer larger than 1;

and

said addition circuits are disposed in parallel in groups of m with coefficient calculation circuits in order to determine a weight value as a single polarity coefficient calculation value according to one of the coefficients or according to a difference between an ith coefficient and an ith input signal with respect to said input signals from 1 to k, where i is an integer from 1 to k and k is an integer larger than 1 and smaller than n, said coefficient calculation circuits including a first coefficient calculation circuit provided in a dedicated fashion for one coefficient and a first addition circuit for conducting accumulation of first to kth outputs of said coefficient calculation circuits; and

further comprising;

a selection control circuit for comparing an intermediate result of m accumulations and a saturation level of said threshold value circuit, determining whether to continue calculation with respect to the input signals of remaining input terminals, and outputting intermediate results of accumulation that are necessary for the continuation of calculation; and

at least one second coefficient calculation circuit and one second addition circuit for use in common with respect to said input terminals for which continuation of calculation is necessary, said input signals and coefficient values are switched and accumulation calculation is continued, said accumulation results corresponding to first to nth input terminals are inputted into said threshold value circuit, and said threshold circuit outputting a processing result.

4. A neural network circuit in accordance with claim 1, wherein

said addition circuit has a plurality n of said input terminals and an identical number of addition circuits;

each said input terminal has a positive value digital input signal as one value to be added in a corresponding addition circuit; and

when i is an integer from 1 to n, an accumulation addition result from (i-1)th addition circuit is used as another value to be added of an ith addition circuit, said addition circuit being an accumulation addition circuit for conducting the accumulation addition of all input signals; and

further comprising;

a gate circuit for controlling input values to be added into the corresponding addition circuits according to a carry signal from an immediately preceding addition circuit, said gate circuit having a value to be added at an input side of said addition circuit; and

means for stopping the accumulation calculations of the ith addition circuit and onward when an accumulation addition result in the (i-1)th addition circuit exceeds a predetermined value.

5. A neural network circuit in accordance with claim 1, wherein

said addition circuit has a plurality n of said input terminals and an identical number of addition circuits;

each said input terminal has a positive value digital input signal as one value to be added in a corresponding addition circuit; and

when i is an integer from 1 to n, an accumulation addition result up to the (i-1)th addition circuit is used as another value to be added of an ith addition circuit, said addition circuit being an accumulation addition circuit for conducting the accumulation addition of all input signals; and

further comprising;

a gate circuit controlled by a carry signal from a previous addition circuit and disposed between all values to be added, input terminals and carry input terminals of a plurality of one bit addition circuits comprising each addition circuit; and

means for stopping the accumulation calculations of the ith addition circuit and onward when an accumulation addition result in the (i-1)th addition circuit exceeds a predetermined value.