Membrane dielectric isolation IC fabrication

• US 5,354,695 A
• Filed: 04/08/1992
• Issued: 10/11/1994
• Est. Priority Date: 04/08/1992
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): Hearn, Brian
• Assistant Examiner(s): DANG, TRUNG Q
• Application Number:
  US07/865,412
• Time in Patent Office: 916 Days
• Field of Search: 437/974, 437/7, 437/8, 437/62, 437/66, 437/238, 437/241, 156/662, 148/DIG. 135
• US Class Current: 438/411
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/136281 having a transmissive semiconductor substrate
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5387 : Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 148/135 : Removal of substrate
• CPC Class Codes: Y10S 438/928 : Front and rear surface processing
• CPC Class Codes: Y10S 438/938 : Lattice strain control or utilization
• CPC Class Codes: Y10S 438/942 : Masking
• CPC Class Codes: Y10S 438/967 : Semiconductor on specified insulator
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49162 : by using wire as conductive path
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49171 : with encapsulating
• CPC Class Codes: Y10T 29/4921 : with bonding

Abstract

General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography,. and 3D IC fabrication.

Claims

1. A method of making an integrated circuit comprising the steps of:

forming a substrate having a thickness of less than about 50 μ

m;

forming semiconductor devices on a principal surface of the substrate;

depositing a low stress insulating membrane over the semiconductor devices wherein said insulating membrane has a net surface tensile stress level 2-100 times less than a fracture strength of the insulating membrane material; and

forming electrical interconnections in the membrane extending between the semiconductor devices.

2. The method of claim 1, further comprising the steps of:

forming an epitaxial layer on the principal surface; and

forming the semiconductor devices in the epitaxial layer.

3. The method of claim 1, further comprising the step of forming a trench in the substrate isolating at least one of the semiconductor devices from the others.

4. The method of claim 1, wherein the step of the forming the substrate comprises electro-chemical etching.

5. The method of claim 1, wherein the step of depositing includes the step of supplying SiH₄ gas, N₂ gas, and N₂ gas at a temperature of about 400°

C.

6. The method of claim 1, wherein the step of depositing includes the step of supplying SiH₄ gas, NH₃ gas and N₂ gas, at a temperature of about 400°

C.

7. The method of claim 1, wherein the substrate comprises polycrystalline silicon.

8. The method of claim 1, wherein the substrate comprises a monocrystalline material.

9. The method of claim 1, wherein the substrate comprises an amorphous material.

10. The method of claim 2, wherein the epitaxial layer includes germanium.

11. The method of claim 1 wherein the substrate has an area greater than 1 square cm.

12. The method of claim 1 wherein the electrical interconnections are formed in the membrane both above and below the semiconductor devices.

13. The method of claim 1 further comprising at least one additional processing step performed at a temperature in excess of 400°

C.

14. The method of claim 13 wherein said additional processing step comprises implant activation annealing.

15. The method of claim 13 wherein said additional processing step comprises epitaxial processing.

16. A method of making an integrated circuit comprising the steps of:

forming a substrate having a thickness of less than about 50 μ

m;

forming semiconductor devices on a principal surface of the substrate;

depositing a low stress insulating membrane over the semiconductor devices wherein said insulating membrane is deposited with a material selected from the group consisting of silicon dioxide and silicon nitride and has a surface stress level of less than 8×

10⁸ dynes/cm² in tension; and

forming electrical interconnections in the membrane extending between the semiconductor devices.