Method of making a lattice mismatched heterostructure optical waveguide

• US 5,354,709 A
• Filed: 04/11/1991
• Issued: 10/11/1994
• Est. Priority Date: 11/10/1986
• Status: Expired due to Fees

• Current Assignee: United States Of America As Represented By The Secretary Of The Air Force
• Original Assignee: United States Of America As Represented By The Secretary Of The Air Force
• Inventors: Soref, Richard A., Lorenzo, Joseph P.
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US07/683,924
• Time in Patent Office: 1,279 Days
• Field of Search: 437/89, 437/132, 437/83, 437/129, 350/96.12, 350/96.14, 357/16, 357/17, 357/55, 357/56, 372/45, 372/46, 372/48, 148/DIG. 26, 148/DIG. 72, 148/DIG. 149, 148/DIG. 152, 257/183, 257/200
• US Class Current: 117/8
• CPC Class Codes: G02B 2006/12061 Silicon
• CPC Class Codes: G02B 2006/12169 Annealing
• CPC Class Codes: G02B 6/122 Basic optical elements, e.g. light-guiding paths
• CPC Class Codes: G02B 6/136 by etching
• CPC Class Codes: Y10S 117/902 Specified orientation, shape, crystallography, or size of seed or substrate
• CPC Class Codes: Y10S 117/918 Single-crystal waveguide
• CPC Class Codes: Y10S 148/026 Deposition thru hole in mask
• CPC Class Codes: Y10S 148/072 Heterojunctions
• CPC Class Codes: Y10S 148/149 Silicon on III-V
• CPC Class Codes: Y10S 148/152 Single crystal on amorphous substrate
• CPC Class Codes: Y10S 438/933 Germanium or silicon or Ge-Si on III-V
• CPC Class Codes: Y10S 438/958 Passivation layer

Abstract

The invention comprises processes and heterostructure products defining silicon on insulator waveguides (80, 88, 90, 106, 112, 120, 122) that are suitable for use with light in the 1.3, 1.6 μm or greater wavelengths. Silicon is deposited on an insulator layer 12 on a crystalline substrate 10 and grown or regrown in crystalline form. The silicon is then etched or formed into a waveguide structures.

Claims

1. A method of producing a heterostructure optical waveguide comprising the steps of:

(a) providing a first crystalline layer of a first semiconductor material;

(b) depositing a dielectric film over said first crystalline layer and having a plurality of seeding windows formed completely therethrough;

(c) producing a second crystalline layer of a second semiconductor material upon said dielectric film, said second layer crystallized by seeding from said first crystalline layer, said second semiconductor material being lattice mismatched with respect to the material of said first crystalline layer, and said second crystalline layer having a major surface covering said dielectric film;

(d) during the performance of step (c), maintaining said second layer in contact with said first layer via said seeding windows;

(e) during the performance of step (c), producing lattice mismatch defects propogating toward said second layer and orthogonally with respect to the major surface of said second crystalline layer, which defects terminate in regions over said seeding windows while seeding lateral crystallization of said second layer parallel to the major surface thereof.

2. The method of claim 1 wherein said first material is a group III-V material.

3. The method of claim 1 wherein said second semiconductor material is Si.

4. The method of claim 3 wherein said dielectric film comprises silicon dioxide.

5. The method of claim 3 wherein said seeding windows are configured as discontinuous stripes.

6. The method of claim 2 wherein said dielectric film comprises silicon dioxide.

7. The method of claim 1 wherein said second semiconductor material is Si.

8. The method of claim 7 wherein said dielectric film comprises silicon dioxide.

9. The method of claim 7 wherein said seeding windows are configured as discontinuous stripes.

10. The method of claim 1 wherein said dielectric film comprises silicon dioxide.

11. The method of claim 1 wherein step (c) includes thermal heating of said second crystalline layer.

12. The method of claim 1 wherein said seeding windows are configured as discontinuous stripes.

13. A method of producing a heterostructure optical waveguide comprising the steps of:

(a) providing a first crystalline layer of a first semiconductor material;

(b) producing a dielectric film covering said first crystalline layer and having a plurality of seeding windows formed completely therethrough;

(c) non-epitaxially joining a second layer of a second material upon said dielectric layer, capable of being crystallized by seeding from said first crystalline layer, and being lattice mismatched with respect to the material of said first crystalline layer, said second crystalline layer having a major surface covering said dielectric film; and

(d) thermally heating said second layer while maintaining said second layer in contact with said first layer via said seeding windows for producing lattice mismatch defects propogating toward said second layer and orthogonally with respect to the major surface of said second crystalline layer, which defects terminate in regions over said seeding windows while seeding lateral crystallization of said second layer parallel to the major surface thereof.

14. The method of claim 13 wherein said first semiconductor material is a group III-V material.

15. The method of claim 14 wherein said dielectric film comprises silicon dioxide.

16. The method of claim 13 wherein said second material initially deposited upon said dielectric film during the performance of step (c) is amorphous or polycrystalline Si.

17. The method of claim 16 wherein said dielectric film comprises silicon dioxide.

18. The method of claim 13 wherein said dielectric film comprises silicon dioxide.

19. The method of claim 18 wherein said dielectric film comprises silicon dioxide.

20. A method of producing a heterostructure optical waveguide comprising the steps of:

(a) providing a first crystalline layer of a first semiconductor material;

(b) producing a dielectric film covering said first crystalline layer and having a plurality of seeding windows formed completely therethrough;

(c) non-epitaxially depositing a second layer of amorphous silicon upon said dielectric film, capable of being crystallized by seeding from said first crystalline layer, and being lattice mismatched with respect to the material of said first crystalline layer, said second crystalline layer having a major surface covering said dielectric film; and

(d) thermally heating said second layer to a sufficient extent to anneal said amorphous silicon and promote epitaxial regrowth thereof while maintaining said second layer in contact with said first layer via said seeding windows for producing lattice mismatch defects propogating toward said second layer and orthogonally with respect to the major surface of said second crystalline layer, which defects terminate in regions over said seeding windows while seeding lateral crystallization of said second layer parallel to the major surface thereof.

21. The method of claim 20 wherein said first semiconductor material is a group III-V material.