Insulated gate field effect transistor having LDD structure and method of making the same including a channel stop having a peak impurity concentration, the channel stop provided below a channel region

• US 5,355,011 A
• Filed: 07/14/1993
• Issued: 10/11/1994
• Est. Priority Date: 07/15/1992
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takata, Osamu
• Primary Examiner(s): Loke, Steven Ho Yin
• Application Number:
  US08/090,934
• Time in Patent Office: 454 Days
• Field of Search: 257/408, 257/409, 257/404, 257/398, 257/399, 257/400, 257/344, 257/394, 257/345
• US Class Current: 257/408
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

Insulated Gate Field Effect Transitor (IGFET) having a reduced channel length without deteriorating an electric field relief effect includes a channel stop, located below a channel region, having a peak impurity concentration. A depth of the peak impurity concentration from the substrate surface is deeper than a bottom surface of source and drain regions that provides an Lightly Doped Drain structure.

Claims

1. A semiconductor device having an Lightly Doped Drain structure comprising:

a semiconductor substrate of a first conductivity type having a surface;

source and drain regions of a second conductivity type provided in said semiconductor substrate to define a channel region therebetween, one of said source and drain regions having a lightly doped region;

a gate insulating film provided over said channel region;

a gate electrode provided over said gate insulating film; and

a channel stop of said first conductivity type, formed below said channel region, having a peak impurity concentration,

a depth of said peak impurity concentration from said surface of said semiconductor substrate being deeper than a bottom surface of one of said source and drain regions, and

said peak impurity concentration being increased as an effective channel length of said channel region is reduced.

2. The semiconductor device according to claim 1, wherein said peak impurity concentration is increased as said depth is increased.

3. The semiconductor device according to claim 1, wherein said depth of said peak impurity concentration of channel stop is deeper than said lightly doped region.