Stacked-type semiconductor device

• US 5,355,022 A
• Filed: 08/28/1992
• Issued: 10/11/1994
• Est. Priority Date: 09/10/1991
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ajika, Natsuo, Iwamatsu, Toshiaki, Ipposhi, Takashi, Sugahara, Kazuyuki, Ogawa, Toshiaki
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): OSTROWSKI, DAVID M
• Application Number:
  US07/936,390
• Time in Patent Office: 774 Days
• Field of Search: 257/686, 257/723, 257/724, 257/754, 257/755, 257/757, 257/760, 257/768, 257/777, 257/506
• US Class Current: 257/768
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

In a method of manufacturing a stacked-type semiconductor device, firstly, a first semiconductor substrate having a first device formed thereon is covered with an interlayer insulating layer and a planarized polycrystalline silicon layer is formed on the interlayer insulating layer. The first semiconductor substrate and a second semiconductor substrate are joined together by putting the surface of the polycrystalline silicon layer in close contact with the surface of a refractory metal layer formed on the second semiconductor substrate, applying thermal treatment at 700° C. or below and changing the refractory metal layer to silicide.

Claims

1. A stacked-type semiconductor device comprising:

a supporting substrate having a main surface;

a refractory metal silicide layer on said main surface of said supporting substrate, said refractory metal silicide layer having an upper surface and a lower surface facing said main surface;

a silicon layer on said upper surface of said refractory metal silicide layer, said silicon layer having an upper surface and a lower surface facing said upper surface of said refractory metal silicide layer;

a first semiconductor layer on said upper surface of said silicon layer, said first semiconductor layer having an upper surface and a lower surface facing said upper surface of said silicon layer; and

a second semiconductor layer on said upper surface of asid first semiconductor layer with an insulating layer interposed therebetween,

wherein said second semiconductor layer has an upper surface and a lower surface, and said lower surface of said first semiconductor layer and said upper surface of said second semiconductor layer each has at least one electronic device formed thereon.

2. A stacked-type semiconductor device according to claim 1, wherein said supporting substrate comprises a silicon substrate.

3. A stacked-type semiconductor device according to claim 1 1, wherein said supporting substrate comprises a quartz substrate.

4. A stacked-type semiconductor device according to claim 1, further comprising an insulating film interposed between said silicon layer and said first semiconductor layer.

5. A stacked-type semiconductor device according to claim 1, wherein at least one of said first and second semiconductor layers is a silicon layer.

6. A stacked-type semiconductor device comprising:

a supporting having a main surface;

a silicon nitride layer on said main surface of said supporting substrate, said silicon nitride layer having an upper surface and a lower surface facing said main surface;

a silicon layer on said upper surface of said silicon nitride layer, said silicon layer having an upper surface and a lower surface facing said upper surface of said silicon nitride layer;

a first semiconductor layer on said upper surface of said silicon layer, said first semiconductor layer having an upper surface and a lower surface facing said upper surface of said silicon layer; and

a second semiconductor layer on said upper surface of said first semiconductor layer with an insulating layer interposed therebetween, said second semiconductor layer having an upper surface and a lower surface,

wherein said lower surface of said first semiconductor layer and said upper surface of said second semiconductor layer each has at least one electronic device formed thereon.

7. A stacked-type semiconductor device according to claim 6, wherein said supporting substrate comprises a silicon substrate.

8. A stacked-type semiconductor device according to claim 6, wherein said supporting substrate comprises a quartz substrate.

9. A stacked-type semiconductor device according to claim 6, further comprising an insulating film interposed between said silicon layer and said first semiconductor layer.

10. A stacked-type semiconductor device according to claim 6, wherein at least one of said first and second semiconductor layers is a silicon layer.