High speed BICMOS switches and multiplexers

• US 5,355,035 A
• Filed: 01/08/1993
• Issued: 10/11/1994
• Est. Priority Date: 01/08/1993
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Dyna Logic Corporation
• Inventors: Vora, Madhukar B., West, Burnell G.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): TRAN, TOAN V
• Application Number:
  US08/002,172
• Time in Patent Office: 641 Days
• Field of Search: 307/494, 307/495, 307/241, 307/242, 307/243, 307/355, 328/104, 328/154, 330/261, 330/252
• US Class Current: 327/433
• CPC Class Codes: H03K 17/6257 with several inputs only combined with selecting means
• CPC Class Codes: H03K 17/6285 with several outputs only combined with selecting means
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence

Abstract

A high speed switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed.

Claims

1. A high speed switch, comprising:

a pair of data inputs for receiving high speed, complementary input signals;

one or more pairs of high speed complementary data outputs;

a high voltage supply;

a low voltage supply;

one or more differential pairs of current mode logic transistors having base terminals coupled to said data inputs, each pair having a pair of collectors coupled to said high voltage supply and to one of said pairs of high speed complementary data outputs, and each pair having emitters coupled to a common node;

an essentially constant current source corresponding to each said differential pair of current mode logic transistors selectively coupling said common node to said low voltage supply;

one or more steering signal inputs, each steering signal input corresponding to one of said differential pairs of current mode logic transistors, each steering signal input for receiving a steering signal; and

enabling means for selectively coupling said constant current source for each said differential coupled pair of current mode transistors to said low voltage supply and for decoupling the common node of each said differential pair to said high voltage supply when the corresponding steering signal is in a first state, and for decoupling said constant current source for each said differential coupled pair of current mode logic transistors from said low voltage supply and coupling the common node of each said differential coupled pair of current mode logic transistors from said high voltage supply when the corresponding steering signal is in a second state, thereby allowing any of said differential coupled pairs of current mode logic transistors to drive the corresponding pair of high speed data outputs under the influence of the high speed data input signals received at said data inputs by control of the states of said steering signals.

2. The apparatus of claim 1 wherein said enabling means comprises for each said differential pair of current mode logic transistors, a PMOS transistor coupling said common node to said high voltage supply, and an NMOS transistor coupling said current source to said low voltage supply, each of said NMOS and PMOS transistors having their gates coupled to said steering signal.

3. A high speed switch comprising:

at least two pairs of high speed data inputs, each pair for receiving a pair of high speed, complementary data signals;

a pair of outputs for outputting a complementary pair of high speed output signals;

a high voltage supply;

a low voltage supply;

a pair of shared pullup resistors coupled to said high voltage supply;

a pair of differential current mode logic transistors, each having a collector coupled to one of said pair of pullup resistors and to one of said outputs of said output pair, and having base terminals each of which is coupled to one of the signal inputs of a selected pair of said high speed data inputs, and having a pair of emitter terminals coupled to a common node;

one or more pairs of differential coupled, current mode logic transistors, each having a collector coupled to one of said outputs of said output pair, and having base terminals each of which is coupled to one of the signal inputs of a selected pair of said high speed data inputs different from the high speed data input pairs coupled to each other said differential coupled pair of current mode logic transistors, each said differential coupled pair of current mode logic transistors having a pair of emitter terminals coupled to a common node;

one or more essentially constant current sources, each for selectively coupling one of said common nodes to said low voltage supply;

one or more steering signal inputs, each for receiving a steering signal for controlling the enabled or disabled state of a corresponding one of said differential coupled pair of current mode logic transistors; and

enabling means for selectively coupling said constant current source for each said differential coupled pair of current mode transistors to said low voltage supply and for decoupling the common node of each said differential pair to said high voltage supply when the corresponding steering signal is in a first state, and for decoupling said constant current source for each said differential coupled pair of current mode logic transistors from said low voltage supply and coupling the common node of each said differential coupled pair of current mode logic transistors from said high voltage supply when the corresponding steering signal is in a second state, thereby allowing any of said differential coupled pairs of current mode logic transistors to drive the corresponding pair of high speed data outputs under the influence of the high speed data input signals received at said data inputs by control of the states of said steering signals.

4. The apparatus of claim 3 wherein said enabling means comprises for each said differential coupled pair of current mode logic transistors, a PMOS transistor coupling said common node to said high voltage supply, and an NMOS transistor coupling said current source to said low voltage supply, each of said NMOS and PMOS transistors having their gates coupled to said steering signal.

5. A high speed, multiplexer comprising:

switching means including first and second differential inputs and a plurality of high speed differential amplifiers, each differential amplifier having a common power return node for selective connection to a low voltage supply, and each differential amplifier coupled to receive high speed data signals from said first and second differential inputs, and each differential amplifier having a pair of differential outputs, said switching means for receiving high speed data signals, and, when enabled, for coupling said high speed data signals to a selected output; and

enabling means having an enable input corresponding to each said differential amplifier including CMOS switching means corresponding to each said differential amplifier and coupled to the enable input and common power return node of the corresponding differential amplifier, said CMOS switching means for selective enabling or disabling the corresponding differential amplifier, said enabling means for enabling the corresponding differential amplifier by selective coupling of each said differential amplifier means common power return node to said low voltage supply via the corresponding CMOS switching means when the corresponding enable input receives an activated enable signal indicating the corresponding differential amplifier is to be rendered operational thereby differentially amplifying the high speed data signals at said first and second differential inputs and outputting the data signals so amplified to the corresponding pair of differential outputs, and for disabling a differential amplifier by coupling said common power return node to a high voltage supply via the corresponding CMOS switching means when the corresponding enable signal is not active.

6. A crossbar switch, comprising:

a first multiplexer having a plurality of data inputs and a shared data output comprised of a plurality of switching devices each of which is coupled to one of said plurality of data inputs and each of which can be individually enabled under the influence of a corresponding steering signal associated with that switching device so as to be able to drive said shared data output in accordance with the data received at the corresponding data input;

one or more other multiplexers each having inputs coupled to the same plurality of data inputs coupled to said first multiplexer, and each having a shared data output, and each comprised of a plurality of switching devices each of which is coupled to one of said plurality of data inputs coupled to a corresponding switching device of said first multiplexer, each of said switching devices of said one or more other multiplexers including enabling circuitry coupled to the associated switching device such that the associated switching device can be individually enabled under the influence of a corresponding steering signal so as to be able to drive the corresponding said shared data output in accordance with the data received at the corresponding data input, such that by proper manipulation of said steering signals for said first multiplexer and said one or more other multiplexers, each of the shared outputs can be driven by any of the data inputs so long as no more than one data input is used to drive any shared data output at any particular time and wherein each of said multiplexers is comprised of;

at least two pairs of high speed data inputs, each pair for receiving a pair of high speed, complementary data signals;

a pair of outputs for outputting a complementary pair of high speed output signals;

a high voltage supply;

a low voltage supply;

a pair of shared pullup resistors coupled to said high voltage supply;

a pair of differential current mode logic transistors, each having a collector coupled to one of said pair of pullup resistors and to one of said outputs of said output pair, and having base terminals each of which is coupled to one of the signal inputs of a selected pair of said high speed data inputs, and having a pair of emitter terminals coupled to a common node;

one or more pairs of different coupled, current mode logic transistors, each having a collector coupled to one of said outputs of said output pair, and having base terminals each of which is coupled to one of the signal inputs of a selected pair of said high speed data inputs different from the high speed data input pairs coupled to each other said differential coupled pair of current mode logic transistors, each said differential coupled pair of current mode logic transistors having a pair of emitter terminals coupled to a common node;

one or more essentially constant current sources, each for selectively coupling one of said common nodes to said low voltage supply;

one or more steering signal inputs, each for receiving a steering signal for controlling the enabled or disabled state of a corresponding one of said differential coupled pair of current mode logic transistors; and

enabling means for selectively coupling said constant current source for each said differential coupled pair of current mode transistors to said low voltage supply and for decoupling the common node of each said differential pair to said high voltage supply when the corresponding steering signal is in a first state, and for decoupling said constant current source for each said differential coupled pair of current mode logic transistors from said low voltage supply and coupling the common node of each said differential coupled pair of current mode logic transistors from said high voltage supply when the corresponding steering signal is in a second state, thereby allowing any of said differential coupled pairs of current mode logic transistors to drive the corresponding pair of high speed data outputs under the influence of the high speed data input signals received at said data inputs by control of the states of said steering signals.