Ball grid array with via interconnection

• US 5,355,283 A
• Filed: 04/14/1993
• Issued: 10/11/1994
• Est. Priority Date: 04/14/1993
• Status: Expired due to Term

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Electronics, Inc. (Amkor Technology Incorporated), Teijin Limited
• Inventors: Hirakawa, Tadashi, Marrs, Robert C.
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): LEDYNH, BOT L
• Application Number:
  US08/047,721
• Time in Patent Office: 545 Days
• Field of Search: 361/728, 361/730, 361/736, 361/760, 361/761, 361/765, 361/767, 361/777, 174/52.2, 174/52.4, 174/260, 174/262, 174/263, 174/264-266, 257/678, 257/684, 257/687, 257/693, 257/698, 257/701, 257/704, 257/774, 257/779, 257/786-788, 29/841, 29/848, 29/855, 29/856
• US Class Current: 361/760
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.

Abstract

A ball grid array is formed by mounting and electrically connecting one or more electronic devices to a substrate in which vias are formed to interconnect electrically conductive traces formed in a surface of the substrate to solder ball pads formed at an opposite surface of the substrate. The vias are formed by mechanical or laser drilling. Solder balls are formed on each of the pads and are reflow-attached to, for instance, a printed circuit board. The electronic components can include one or more integrated circuit chips, as well as passive components. The electronic components are attached to the substrate using wirebonding, TAB or flip chip connection. An encapsulating material is applied to encapsulate the electronic devices.

Claims

1. A packaged integrated circuit, comprising:

a substrate having first and second opposed surfaces, electrically conductive first traces being formed on the first surface of the substrate;

a series of electrically conductive pads extending across a portion of the substrate opposite the first surface of the substrate;

a series of vias formed in the substrate, each via extending to one of said pads;

electrically conductive plating material on sidewalls of said vias in electrical contact with selected ones of said first traces and with selected ones of said pads;

an electronic device attached to the first surface of the substrate;

means for making electrical connection between the electronic device and at least one of the first traces on the substrate; and

encapsulant formed around the electronic device so as to protect the electronic device, the encapsulant covering at least a portion of the first surface of the substrate, filling said vias and extending against a via-facing surface of said pads.

2. The packaged integrated circuit of claim 1, wherein solder balls are attached to pads at a position juxtaposed to the second surface of the substrate.

3. The packaged integrated circuit of claim 1, wherein said vias are in the form of an inverted truncated cone.

4. The packaged integrated circuit of claim 1, wherein said vias have tapered sidewalls converging toward said pads.

5. The packaged integrated circuit of claim 1, wherein the vias are formed by laser drilling.

6. The packaged integrated circuit of claim 5, wherein the laser is an excimer laser.

7. The packaged integrated circuit of claim 1, wherein electrically non-conductive portions of the substrate are made of organic material.

8. The packaged integrated circuit of claim 7, wherein the organic material includes organic reinforcement fibers.

9. The packaged integrated circuit of claim 8, where the reinforcement fibers are aramid fibers.

10. A method of forming a package integrated circuit comprising the steps of:

fabricating a substrate having a first surface and an opposed second surface;

forming a series of electrically conductive first traces on said first surface;

forming a series of electrically conductive pads extending across a portion of the substrate opposite to said first surface;

then forming a series of vias through said substrate to a via-facing surface of the pads;

depositing a conductive plating in said vias and extending from selected ones of said first traces to selected ones of said pads;

attaching an electronic device to said first surface;

electrically connecting the electronic device to said first traces; and

encapsulating the electronic device with an electrically insulating encapsulant so as to protect the electronic device, the encapsulant covering at least part of said first surface, filling said vias and extending against said via-facing surface of said pads.

11. A method as in claim 10, further comprising forming a solder ball on a surface of each of said pads which faces away from the vias.

12. A method as in claim 10, wherein all first traces on the first surface and the plating in said vias are covered by the encapsulant.

13. A method as in claim 10, wherein vias are formed by laser drilling down to said via-facing surface of said pads.

14. A method as in claim 13, wherein the laser drilling is excimer laser drilling.

15. A method as in claim 10, wherein electrically non-conductive portions of the substrate are made of organic material.

16. A method as in claim 15, wherein the organic material includes organic reinforcement fibers.

17. A method as in claim 16, where the reinforcement fibers are aramid fibers.