Three-level three-phase inverter apparatus

• US 5,355,297 A
• Filed: 04/13/1993
• Issued: 10/11/1994
• Est. Priority Date: 04/13/1992
• Status: Expired due to Term

• Current Assignee: Toshiba Mitsubishi-Electric Industrial Systems Corporation (Toshiba Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Kawabata, Takao, Koyama, Masato
• Primary Examiner(s): Stephan, Steven L.
• Assistant Examiner(s): Berhane, Adolf D.
• Application Number:
  US08/047,043
• Time in Patent Office: 546 Days
• Field of Search: 363/40, 363/41, 363/43, 363/56, 363/58, 363/95, 363/97, 363/98, 363/131, 363/132
• US Class Current: 363/43
• CPC Class Codes: H02M 7/487 Neutral point clamped inverters
• CPC Class Codes: H02P 27/14 with three or more levels of voltage

Abstract

A three-level three-phase inverter apparatus operating on a proposed pulse width modulation method whereby good output voltages are obtained free of the effects of the minimum pulse width constraints of switching devices and whereby the neutral point voltage is controlled. The apparatus has a modulation circuit containing a microprocessor and a voltage vector selection circuit. The microprocessor divides one period into six segments of 60 degrees each. Each segment is divided into four triangular regions each determined by the vertexes of voltage vectors. An output voltage command is given as a vector. Once the segment and region to which a given vector belongs are determined, the voltage vectors corresponding to that region and the order in which to output these vectors are derived from the predetermined vector combinations and their output orders stored beforehand in the voltage vector selection circuit. Each vector output order is arranged so that one voltage vector is replaced by another through a switching operation of any one phase. The time average of these consecutively output voltage vectors in a given carrier period is modulated to coincide with the value of the command vector. This scheme provides good output voltage waveforms while controlling the neutral point voltage.

Claims

1. A three-level three-phase inverter apparatus comprising a three-level inverter for each of U, V and W phases, each three-level inverter comprising:

a direct current power supply having a neutral point output terminal and including a first, a second, a third and a fourth switching device connected in series between the positive and negative electrodes of said direct power supply, the junction between said first and said second switching devices and the junction between said third and said fourth switching devices being each connected to said neutral point output terminal via a clamp device, the junction between said second and said third switching devices constituting an inverter output terminal, wherein P represents the state in which said first and said second switching devices are turned on, 0 stands for the state in which said second and said third switching devices are turned on, and N denotes the state in which said third and said fourth switching devices are turned on;

the switching states of each phase determining voltage vectors of which three contiguous vertexes constitute a region;

voltage vector selecting means for preselecting at least three voltage vectors constituting each vertex of the region, for determining beforehand the order in which to output the voltage vectors within a carrier period, and for storing the voltage vectors and the voltage vector output order;

voltage command generating means for outputting a voltage command in vector format;

region determining means for receiving the voltage command in order to determine the region to which the voltage command is positioned per carrier period;

operation time determining means for determining the allocation of operation times within the carrier period of each voltage vector selected for the region determined by said region determining means so that an inverter output voltage will coincide with the voltage command; and

switching signal generating means for outputting a signal for driving the switching devices of each phase based on the operation time for each voltage vector.

2. A three-level three-phase inverter apparatus according to claim 1, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are switched from one vector to another within the switching time for any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

3. A three-level three-phase inverter apparatus according to claim 1, wherein said voltage vectors are divided into a positive vector group and a negative vector group, said positive vector group having two switching states P and 0, said negative vector group having two switching states N and 0, said voltage vector output order stored in said voltage vector selecting means being composed mixedly of vectors from both groups for consecutive output within a predetermined carrier period, whereby the fluctuation of the potential at said neutral point of said direct current power supply is suppressed.

4. A three-level three-phase inverter apparatus according to claim 2, wherein said voltage vectors are divided into a positive vector group and a negative vector group, said positive vector group having two switching states P and 0, said negative vector group having two switching states N and 0, said voltage vector output order stored in said voltage vector selecting means being composed mixedly of vectors from both groups for consecutive output within a predetermined carrier period, whereby the fluctuation of the potential at said neutral point of said direct current power supply is suppressed.

5. A three-level three-phase inverter apparatus according to claim 3, wherein the voltage vectors in said positive and said negative vector groups are controlled in operation time allocation so as to suppress the fluctuation of the potential at said neutral point of said direct current power supply.

6. A three-level three-phase inverter apparatus according to claim 4, wherein the voltage vectors in said positive and said negative vector groups are controlled in operation time allocation so as to suppress the fluctuation of the potential at said neutral point of said direct current power supply.

7. A three-level three-phase inverter apparatus according to claim 1, wherein said voltage vector selecting means classifies as one group the voltage vectors equal in vector magnitude and in zero-phase voltage.

8. A three-level three-phase inverter apparatus according to claim 7, wherein the voltage vectors are classified into the following groups:

space="preserve" listing-type="tabular">______________________________________ Name of each voltage vector Voltage vector symbol represented by symbol ______________________________________ PPP →

0.sub.P 000 →

0 NNN →

0.sub.N P00, 0P0, 00P →

a.sub.P PP0, 0PP, P0P →

b.sub.P 0NN, N0N, NN0 →

a.sub.N 00N, N00, 0N0 →

b.sub.N P0N, 0PN, NP0, N0P, 0NP, PN0 →

c PNN, NPN, NNP →

a PPN, NPP, PNP →

b ______________________________________

9. A three-level three-phase inverter apparatus according to claim 1, wherein a given region of the voltage vectors stored in said voltage vector selecting means is divided into a plurality of subregions, each of said subregions being assigned a different combination of voltage vectors to be consecutively output within a carrier period, whereby the minimum on- and off-times of said switching devices are kept above a predetermined value each.

10. A three-level three-phase inverter apparatus according to claim 2, wherein a given region of the voltage vectors stored in said voltage vector selecting means is divided into a plurality of subregions, each of said subregions being assigned a different combination of voltage vectors to be consecutively output within a carrier period, whereby the minimum on- and off-times of said switching devices are kept above a predetermined value each.

11. A three-level three-phase inverter apparatus according to claim 3, wherein a given region of the voltage vectors stored in said voltage vector selecting means is divided into a plurality of subregions, each of said subregions being assigned a different combination of voltage vectors to be consecutively output within a carrier period, whereby the minimum on- and off-times of said switching devices are kept above a predetermined value each.

12. A three-level three-phase inverter apparatus according to claim 4, wherein a given region of the voltage vectors stored in said voltage vector selecting means is divided into a plurality of subregions, each of said subregions being assigned a different combination of voltage vectors to be consecutively output within a carrier period, whereby the minimum on- and off-times of said switching devices are kept above a predetermined value each.

13. A three-level three-phase inverter apparatus according to claim 5, wherein a given region of the voltage vectors stored in said voltage vector selecting means is divided into a plurality of subregions, each of said subregions being assigned a different combination of voltage vectors to be consecutively output within a carrier period, whereby the minimum on- and off-times of said switching devices are kept above a predetermined value each.

14. A three-level three-phase inverter apparatus according to claim 6, wherein a given region of the voltage vectors stored in said voltage vector selecting means is divided into a plurality of subregions, each of said subregions being assigned a different combination of voltage vectors to be consecutively output within a carrier period, whereby the minimum on- and off-times of said switching devices are kept above a predetermined value each.

15. A three-level three-phase inverter apparatus according to claim 7, wherein a given region of the voltage vectors stored in said voltage vector selecting means is divided into a plurality of subregions, each of said subregions being assigned a different combination of voltage vectors to be consecutively output within a carrier period, whereby the minimum on- and off-times of said switching devices are kept above a predetermined value each.

16. A three-level three-phase inverter apparatus according to claim 8, wherein a given region of the voltage vectors stored in said voltage vector selecting means is divided into a plurality of subregions, each of said subregions being assigned a different combination of voltage vectors to be consecutively output within a carrier period, whereby the minimum on- and off-times of said switching devices are kept above a predetermined value each.

17. A three-level three-phase inverter apparatus according to claim 9, wherein the voltage vectors are classified into the groups listed below;

and wherein the region containing the origin of the coordinates for the voltage vectors are divided into a first, a second and a third subregion;

said first subregion having voltage vectors 0_P, b_P, a_P, 0₀, b_N, a_N and 0N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the first subregion voltage vectors being below a predetermined value each;

said second subregion having voltage vectors a_P, 0₀, b_N and a_N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the second subregion voltage vectors being above a predetermined value each, the angles of said second subregion voltage vectors ranging from the approximate center of said second subregion to any one of two voltage vectors a_P and a_N ;

said third subregion having voltage vectors b_P, a_P, 0₀ and b_N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the third subregion voltage vectors being above a predetermined value each, the angles of said third region voltage vectors ranging from the approximate center of said third subregion to any one of two voltage vectors b_P and b_N ;

space="preserve" listing-type="tabular">______________________________________ Name of each voltage vector Voltage vector symbol represented by symbol ______________________________________ PPP →

0.sub.p 000 →

0 NNN →

0N P00, 0P0, 00P →

a.sub.P PP0, 0PP, P0P →

b.sub.P 0NN, N0N, NN0 →

a.sub.N 00N, N00, 0N0 →

b.sub.N P0N, 0PN, NP0, N0P, 0NP, PN0 →

c PNN, NPN, NNP →

a PPN, NPP, PNP →

b ______________________________________

18. A three-level three-phase inverter apparatus according to claim 10, wherein the voltage vectors are classified into the groups listed below;

and wherein the region containing the origin of the coordinates for the voltage vectors are divided into a first, a second and a third subregion;

said first subregion having voltage vectors 0_P, b_P, a_P, 0₀, b_N, a_N and 0_N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the first subregion voltage vectors being below a predetermined value each;

said second subregion having voltage vectors a_P, 0₀, b_N and a_N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the second subregion voltage vectors being above a predetermined value each, the angles of said second subregion voltage vectors ranging from the approximate center of said second subregion to any one of two voltage vectors a_P and a_N ;

said third subregion having voltage vectors b_P, a_P, 0₀ and b_N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the third subregion voltage vectors being above a predetermined value each, the angles of said third region voltage vectors ranging from the approximate center of said third subregion to any one of two voltage vectors b_P and b_N ;

space="preserve" listing-type="tabular">______________________________________ Name of each voltage vector Voltage vector symbol represented by symbol ______________________________________ PPP →

0.sub.P 000 →

0 NNN →

0.sub.N P00, 0P0, 00P →

a.sub.P PP0, 0PP, P0P →

b.sub.P 0NN, N0N, NN0 →

a.sub.N 00N, N00, 0N0 →

b.sub.N P0N, 0PN, NP0, N0P, 0NP, PN0 →

c PNN, NPN, NNP →

a PPN, NPP, PNP →

b ______________________________________

19. A three-level three-phase inverter apparatus according to claim 11, wherein the voltage vectors are classified into the groups listed below;

and wherein the region containing the origin of the coordinates for the voltage vectors are divided into a first, a second and a third subregion;

said first subregion having voltage vectors 0_P, b_P, a_P, 0₀, b_N, a_N and 0_N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the first subregion voltage vectors being below a predetermined value each;

said second subregion having voltage vectors a_P, 0₀, b_N and a_N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the second subregion voltage vectors being above a predetermined value each, the angles of said second subregion voltage vectors ranging from the approximate center of said second subregion to any one of two voltage vectors a_P and a_N ;

said third subregion having voltage vectors b_P, a_P, 0₀ and b_N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the third subregion voltage vectors being above a predetermined value each, the angles of said third region voltage vectors ranging from the approximate center of said third subregion to any one of two voltage vectors b_P and b_N ;

space="preserve" listing-type="tabular">______________________________________ Name of each voltage vector Voltage vector symbol represented by symbol ______________________________________ PPP →

0.sub.P 000 →

0 NNN →

0.sub.N P00, 0P0, 00P →

a.sub.P PP0, 0PP, P0P →

b.sub.P 0NN, N0N, NN0 →

a.sub.N 00N, N00, 0N0 →

b.sub.N P0N, 0PN, NP0, N0P, 0NP, PN0 →

c PNN, NPN, NNP →

a PPN, NPP, PNP →

b ______________________________________

20. A three-level three-phase inverter apparatus according to claim 12, wherein the voltage vectors are classified into the groups listed below;

and wherein the region containing the origin of the coordinates for the voltage vectors are divided into a first, a second and a third subregion;

said first subregion having voltage vectors 0_P, b_P, a_P, 0₀, b_N, a_N and 0_N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the first subregion voltage vectors being below a predetermined value each;

said second subregion having voltage vectors a_P, 0₀, b_N and a_N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the second subregion voltage vectors being above a predetermined value each, the angles of said second subregion voltage vectors ranging from the approximate center of said second subregion to any one of two voltage vectors a_P and a_N ;

said third subregion having voltage vectors b_P, a_P, 0₀ and b_N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the third subregion voltage vectors being above a predetermined value each, the angles of said third region voltage vectors ranging from the approximate center of said third subregion to any one of two voltage vectors b_P and b_N ;

space="preserve" listing-type="tabular">______________________________________ Name of each voltage vector Voltage vector symbol represented by symbol ______________________________________ PPP →

0.sub.p 000 →

0 NNN →

0.sub.N P00, 0P0, 00P →

a.sub.P PP0, 0PP, P0P →

b.sub.P 0NN, N0N, NN0 →

a.sub.N 00N, N00, 0N0 →

b.sub.N P0N, 0PN, NP0, N0P, 0NP, PN0 →

c PNN, NPN, NNP →

a PPN, NPP, PNP →

b ______________________________________

21. A three-level three-phase inverter apparatus according to claim 13, wherein the voltage vectors are classified into the groups listed below;

and wherein the region containing the origin of the coordinates for the voltage vectors are divided into a first, a second and a third subregion;

said first subregion having voltage vectors 0_P, b_P, a_P, 0₀, b_N, a_N and 0_N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the first subregion voltage vectors being below a predetermined value each;

said second subregion having voltage vectors a_P, 0₀, b_N and a_N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the second subregion voltage vectors being above a predetermined value each, the angles of said second subregion voltage vectors ranging from the approximate center of said second subregion to any one of two voltage vectors a_P and a_N ;

said third subregion having voltage vectors b_P, a_P, 0₀ and b_N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the third subregion voltage vectors being above a predetermined value each, the angles of said third region voltage vectors ranging from the approximate center of said third subregion to any one of two voltage vectors b_P and b_N ;

space="preserve" listing-type="tabular">______________________________________ Name of each voltage vector Voltage vector symbol represented by symbol ______________________________________ PPP →

0.sub.p 000 →

0 NNN →

0.sub.N P00, 0P0, 00P →

a.sub.P PP0, 0PP, P0P →

b.sub.P 0NN, N0N, NN0 →

a.sub.N 00N, N00, 0N0 →

b.sub.N P0N, 0PN, NP0, N0P, 0NP, PN0 →

c PNN, NPN, NNP →

a PPN, NPP, PNP →

b ______________________________________

22. A three-level three-phase inverter apparatus according to claim 14, wherein the voltage vectors are classified into the groups listed below;

and wherein the region containing the origin of the coordinates for the voltage-vectors are divided into a first, a second and a third subregion;

said first subregion having voltage vectors 0_P, b_P, a_P, 0₀, b_N, a_N and 0_N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the first subregion voltage vectors being below a predetermined value each;

said second subregion having voltage vectors a_P, 0₀, b_N and a_N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the second subregion voltage vectors being above a predetermined value each, the angles of said second subregion voltage vectors ranging from the approximate center of said second subregion to any one of two voltage vectors a_P and a_N ;

said third subregion having voltage vectors b_P, a_P, 0₀ and b_N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the third subregion voltage vectors being above a predetermined value each, the angles of said third region voltage vectors ranging from the approximate center of said third subregion to any one of two voltage vectors b_P and b_N ;

space="preserve" listing-type="tabular">______________________________________ Name of each voltage vector Voltage vector symbol represented by symbol ______________________________________ PPP →

0.sub.P 000 →

0 NNN →

0.sub.N P00, 0P0, 00P →

a.sub.P PP0, 0PP, P0P →

b.sub.P 0NN, N0N, NN0 →

a.sub.N 00N, N00, 0N0 →

b.sub.N P0N, 0PN, NP0, N0P, 0NP, PN0 →

c PNN, NPN, NNP →

a PPN, NPP, PNP →

b ______________________________________

23. A three-level three-phase inverter apparatus according to claim 15, wherein the voltage vectors are classified into the groups listed below;

and wherein the region containing the origin of the coordinates for the voltage vectors are divided into a first, a second and a third subregion;

said first subregion having voltage vectors 0_P, b_P, a_P, 0₀, b_N, a_N and 0_N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the first subregion voltage vectors being below a predetermined value each;

said second subregion having voltage vectors a_P, 0₀, b_N and a_N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the second subregion voltage vectors being above a predetermined value each, the angles of said second subregion voltage vectors ranging from the approximate center of said second subregion to any one of two voltage vectors a_P and a_N ;

said third subregion having voltage vectors b_P, a_P, 0₀ and b_N arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the absolute values of the third subregion voltage vectors being above a predetermined value each, the angles of said third region voltage vectors ranging from the approximate center of said third subregion to any one of two voltage vectors b_P and b_N ;

space="preserve" listing-type="tabular">______________________________________ Name of each voltage vector Voltage vector symbol represented by symbol ______________________________________ PPP →

0.sub.P 000 →

0 NNN →

0.sub.N P00, 0P0, 00P →

a.sub.P PP0, 0PP, P0P →

b.sub.P 0NN, N0N, NN0 →

a.sub.N 00N, N00, 0N0 →

b.sub.N P0N, 0PN, NP0, N0P, 0NP, PN0 →

c PNN, NPN, NNP →

a PPN, NPP, PNP →

b ______________________________________

24. A three-level three-phase inverter apparatus according to claim 17, wherein the region formed by one of the voltage vectors a_P and a_N, by one of the voltage vectors b_P and b_N, and by the voltage vector c is divided into a fourth and a fifth subregion;

said fourth subregion having the voltage vectors a_N, b_N, C and a_P arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the angles of the fourth subregion voltage vectors ranging from the approximate center of said fourth subregion to any one of two voltage vectors a_P and a_N ;

said fifth subregion having the voltage vectors b_N, c, a_P and b_P arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the angles of the fifth subregion voltage vectors ranging from the approximate center of said fifth subregion to any one of two voltage vectors b_P and b_N.

25. A three-level three-phase inverter apparatus according to claim 18, wherein the region formed by one of the voltage vectors a_P and a_N, by one of the voltage vectors b_P and b_N, and by the voltage vector c is divided into a fourth and a fifth subregion;

said fourth subregion having the voltage vectors a_N, b_N, c and a_P arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the angles of the fourth subregion voltage vectors ranging from the approximate center of said fourth subregion to any one of two voltage vectors aP and a_N ;

said fifth subregion having the voltage vectors b_N, c, a_P and b_P arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the angles of the fifth subregion voltage vectors ranging from the approximate center of said fifth subregion to any one of two voltage vectors b_P and b.sub. N.

26. A three-level three-phase inverter apparatus according to claim 19, wherein the region formed by one of the voltage vectors a_P and a_N, by one of the voltage vectors b_P and b_N, and by the voltage vector c is divided into a fourth and a fifth subregion;

said fourth subregion having the voltage vectors a_N, b_N, c and a_P arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the angles of the fourth subregion voltage vectors ranging from the approximate center of said fourth subregion to any one of two voltage vectors a_P and a_N ;

said fifth subregion having the voltage vectors b_N, c, a_P and b_P arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the angles of the fifth subregion voltage vectors ranging from the approximate center of said fifth subregion to any one of two voltage vectors b_P and b_N.

27. A three-level three-phase inverter apparatus according to claim 20, wherein the region formed by one of the voltage vectors a_P and a_N, by one of the voltage vectors b_P and b_N, and by the voltage vector c is divided into a fourth and a fifth subregion;

said fourth subregion having the voltage vectors a_N, b_N, c and a_P arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the angles of the fourth subregion voltage vectors ranging from the approximate center of said fourth subregion to any one of two voltage vectors a_P and a_N ;

said fifth subregion having the voltage vectors b_N, c, a_P and b_P arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the angles of the fifth subregion voltage vectors ranging from the approximate center of said fifth subregion to any one of two voltage vectors b_P and b_N.

28. A three-level three-phase inverter apparatus according to claim 21, wherein the region formed by one of the voltage vectors a_P and a_N, by one of the voltage vectors b_P and b_N, and by the voltage vector c is divided into a fourth and a fifth subregion;

said fourth subregion having the voltage vectors a_N, b_N, c and a_P arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the angles of the fourth subregion voltage vectors ranging from the approximate center of said fourth subregion to any one of two voltage vectors a_P and a_N ;

said fifth subregion having the voltage vectors b_N, c, a_P and b_P arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the angles of the fifth subregion voltage vectors ranging from the approximate center of said fifth subregion to any one of two voltage vectors b_P and b_N.

29. A three-level three-phase inverter apparatus according to claim 22, wherein the region formed by one of the voltage vectors a_P and a_N, by one of the voltage vectors b_P and b_N, and by the voltage vector c is divided into a fourth and a fifth subregion;

said fourth subregion having the voltage vectors a_N, b_N, c and a_P arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the angles of the fourth subregion voltage vectors ranging from the approximate center of said fourth subregion to any one of two voltage vectors a_P and a_N ;

said fifth subregion having the voltage vectors b_N, c, a_P and b_P arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the angles of the fifth subregion voltage vectors ranging from the approximate center of said fifth subregion to any one of two voltage vectors b_P and b_N.

30. A three-level three-phase inverter apparatus according to claim 23, wherein the region formed by one of the voltage vectors a_P and a_N, by one of the voltage vectors b_P and b_N, and by the voltage vector c is divided into a fourth and a fifth subregion;

said fourth subregion having the voltage vectors a_N, b_N, c and a_P arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the angles of the fourth subregion voltage vectors ranging from the approximate center of said fourth subregion to any one of two voltage vectors a_P and a_N ;

said fifth subregion having the voltage vectors b_N, c, a_P and b_P arranged therein for output therefrom in one of two orders alternately, one order being in the forward direction and the other in the reverse direction, the angles of the fifth subregion voltage vectors ranging from the approximate center of said fifth subregion to any one of two voltage vectors b_P and b_N.

31. A three-level three-phase inverter apparatus according to claim 9, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

32. A three-level three-phase inverter apparatus according to claim 10, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

33. A three-level three-phase inverter apparatus according to claim 11, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

34. A three-level three-phase inverter apparatus according to claim 12, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

35. A three-level three-phase inverter apparatus according to claim 13, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

36. A three-level three-phase inverter apparatus according to claim 14, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

37. A three-level three-phase inverter apparatus according to claim 15, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

38. A three-level three-phase inverter apparatus according to claim 16, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

39. A three-level three-phase inverter apparatus according to claim 17, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

40. A three-level three-phase inverter apparatus according to claim 18, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

41. A three-level three-phase inverter apparatus according to claim 19, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

42. A three-level three-phase inverter apparatus according to claim 20, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

43. A three-level three-phase inverter apparatus according to claim 21, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

44. A three-level three-phase inverter apparatus according to claim 22, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

45. A three-level three-phase inverter apparatus according to claim 23, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

46. A three-level three-phase inverter apparatus according to claim 24, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

47. A three-level three-phase inverter apparatus according to claim 25, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

48. A three-level three-phase inverter apparatus according to claim 26, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

49. A three-level three-phase inverter apparatus according to claim 27, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to No

50. A three-level three-phase inverter apparatus according to claim 28, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

51. A three-level three-phase inverter apparatus according to claim 29, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.

52. A three-level three-phase inverter apparatus according to claim 30, wherein the voltage vectors contiguous in said voltage vector output order stored in said voltage vector selecting means are such that between two contiguous regions, one voltage vector is replaced by another through a switching operation of any one phase, the switching being accomplished in any one of two transitions, one from P to 0 and the other from 0 to N.