Dynamic reference system for sense amplifier

• US 5,355,333 A
• Filed: 10/12/1993
• Issued: 10/11/1994
• Est. Priority Date: 09/26/1991
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Inventors: Pascucci, Luigi
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Nguyen, Tan
• Application Number:
  US08/135,842
• Time in Patent Office: 364 Days
• Field of Search: 307/530, 307/360, 365/189.01, 365/189.09, 365/207, 365/208, 365/210
• US Class Current: 365/189.15
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A dynamic reference system for a sense-amplifier is implemented by using an asymmetric pair of transistors (one twice the size of the other) in the current paths between two selected sensing lines and a source of a bias current in order to superimpose an offset current to the currents forced through the loads of the two sensing lines. The asymmetric transistors may be driven by the signals which are generated by a pair of cascode circuits which are normally used to drive the load-connecting switches of the sensing network or by the signals present on the "other one" of the two sensing lines. This introduces a dynamic behavior of the reference system during an evaluation phase of a reading cycle which follows a first capacitance-charging phase, thus enhancing overall discrimination performances of the sense amplifier. The reference system is simple to implement and offers a number of advantages as compared to "static" reference systems of the prior art.

Claims

1. A reference circuit for reading memory cells through a current unbalance between a first current forced through a first sensing line, containing a reference cell, and a second current forced through a second sensing line, containing a memory cell selected for a reading, of an input network of a differential amplifier, wherein each of said two lines is connected to an essentially identical load and wherein a first high impedance amplifying stage circuit has an input connected to said first line and a second high impedance amplifying stage circuit has an input connected to said second line, each of said amplifying circuits generating on a respective output node a signal which is utilized for driving at least a switch connected between a respective load and a source of a bias current forced through said sensing lines, comprising

a first transistor functionally connected between said switch driven by the first high impedance amplifying circuit and said source of a bias current and having a control terminal which is connected to said output node of said first high impedance amplifying circuit;

a second transistor functionally connected between said switch driven by said second high impedance amplifying circuit and said source of bias current and having a control terminal which is connected to said output node of said second high impedance amplifying circuit;

said first and second transistors having different sizes from each other and driven by said signals generated on the respective output nodes of said high impedance amplifying circuits superimposing an offset current on said currents which are forced through said identical loads of said two sensing lines of the input network of said differential amplifier.

2. A reference circuit as defined in claim 1, wherein said source of bias current is constituted by a current generator connected between a common source node of said first and second transistors having a size different from each other and a ground node of the circuit.

3. A reference circuit as defined in claim 2, wherein said generator of a bias current delivers a current which is identical to the current of a virgin memory cell.

4. A reference circuit as defined in claim 1, wherein said first transistor has twice the size of said second transistor.

5. A reference circuit according to claim 4, wherein said second transistor has a size identical to the size of transistors constituting said switches.

6. A reference circuit as defined in claim 1, wherein said source of bias current for the load of said first sensing line is constituted by said first transistor, a source of which is connected to a ground node of the circuit and said source of bias current for the load of said second sensing line is constituted by said second transistor, a source of which is connected to said ground node.

7. A reference circuit as defined in claim 1, wherein said memory cells are organized in a NOR configuration.

8. A reference circuit as defined in claim 1, wherein said memory cells are organized in an AND configuration.

9. A reference circuit as defined in claim 1, wherein said reference memory cells are non-conducting.

10. An electrically programmable memory device, comprising a plurality of electrically programmable memory cells in combination with the reference circuit of claim 1.

11. A reference circuit for reading memory cells through a current unbalance between a first current forced through a first sensing line, containing a reference cell, and a second current forced through a second sensing line, containing a memory cell selected for a reading, of an input network of a differential amplifier, wherein each of said two lines is connected to an essentially identical load and wherein a first high impedance amplifying stage circuit has an input connected to said first line and a second high impedance amplifying stage circuit has an input connected to said second line, each of said amplifying circuits generating on a respective output node a signal which is utilized for driving at least a switch connected between a respective load and a source of a bias current forced through said sensing lines, and further comprising

a first transistor functionally connected between said switch driven by the first high impedance amplifying circuit and said source of a bias current and having a control terminal which is connected to said second sensing line;

a second transistor functionally connected between said switch driven by said second high impedance amplifying circuit and said source of a bias current and having a control terminal which is connected to said first sensing line;

said first and second transistors having different sizes from each other and driven by signals present on the relatively opposite one of said two sensing lines superimposing an offset current on said currents which are forced through said identical loads of said two sensing lines of the input network of said differential sense-amplifier.

12. A reference circuit as defined in claim 11, wherein said source of a bias current is constituted by a current generator connected between a common source node of said first and second transistors having a size different from each other and a ground node of the circuit.

13. A reference circuit as defined in claim 12, wherein said generator of a bias current delivers a current which is identical to the current of a virgin memory cell.

14. A reference circuit as defined in claim 11, wherein said first transistor has twice the size of said second transistor.

15. A reference circuit according to claim 14, wherein said second transistor has a size identical to the size of transistors constituting said switches.

16. A reference circuit as defined in claim 11, wherein a said source of bias current for the load of said first sensing line is constituted by said first transistor, a source of which is connected to a ground node of the circuit and said source of bias current for the load of said second sensing line is constituted by said second transistor, a source of which is connected to said ground node.

17. A reference circuit as defined in claim 11, wherein said memory cells are organized in a NOR configuration.

18. A reference circuit as defined in claim 11, wherein said memory cells are organized in an AND configuration.

19. A reference circuit as defined in claim 11, wherein said reference memory cells are non-conducting.

20. An electrically programmable memory device, comprising a plurality of electrically programmable memory cells in combination with the reference circuit of claim 11.

21. A method for implementing a dynamic reference system for reading memory cells through a current unbalance between a first current forced through a first sensing line, containing a reference cell, and a second current forced through a second sensing line, containing a memory cell selected for a reading, of an input network of a differential amplifier, wherein each of said two lines is connected to an essentially identical load and wherein a first high impedance amplifying stage circuit has an input connected to said first line and a second high impedance amplifying stage circuit has an input connected to said second line, each of said amplifying circuits generating on a respective output node a signal which is utilized for driving at least a switch connected between a respective load and a source of a bias current forced through said sensing lines bias current, which comprises utilizing said signals generated on the respective output nodes by said high impedance amplifying circuits for driving two asymmetric transistors respectively which are functionally connected between said switches, respectively and said bias current source and have different sizes from each other, for superimposing an offset current on said currents forced through the loads of said sensing lines.

22. A method for implementing a dynamic reference system for reading memory cells through a current unbalance between a first current forced through a first sensing line, containing a reference cell, and a second current forced through a second sensing line, containing a memory cell selected for a reading, of an input network of a differential amplifier, wherein each of said two lines is connected to an essentially identical load and wherein a first high impedance amplifying stage circuit has an input connected to said first line and a second high impedance amplifying stage circuit has an input connected to said second line, each of said amplifying circuits generating on a respective output node a signal which is utilized for driving at least a switch connected between a respective load and a source of a bias current forced through said sensing lines and which comprises

utilizing a signal present on the connection node to the respective load of said first sensing line for driving a first asymmetric transistor functionally connected between said switch and said bias current source of said second sensing line;

utilizing a signal present on the connection node to the respective load of said second sensing line for driving a second asymmetric transistor functionally connected between said switch and said bias current source of said first sensing line;

said first and second asymmetric transistors having different sizes from each other.

23. An integrated circuit memory, comprising:

a plurality of reference cells each programmed to a known state, and each connected to a reference bit line;

a sense amplifier comprising

a matrix side connectable to a selected one of said matrix bit lines, and a reference side connectable to said reference bit line, each said side including;

an input node connectable to said respective bit line;

an amplifier having its input connected to said input node;

an offset transistor connected to provide a controlled current to said input node from a first power supply node;

a pass transistor connected between said input node and an output node, and connected to be driven by said amplifier;

a load element, connected to provide a controlled current to said output node from a second power supply node;

wherein said offset transistor of said matrix side and said offset transistor of said reference side have respective sizes which are unequal;

equalization logic connected to equate the potential of at least a portion of said first side to the potential of a corresponding portion of said second side, when an equalization signal is input thereto; and

a differential amplifier connected to receive said output nodes of said first and second sides of said sense amplifier, and configured to provide a corresponding output signal.

24. The integrated circuit of claim 23, further comprising selection logic configured to connect said sense amplifier to only a selected one of said matrix bit lines.

25. The integrated circuit of claim 23, wherein said equalization logic comprises a first equalization transistor connected to equalize said output nodes, and a second transistor connected to equalize the gate potentials of said pass transistors.

26. The integrated circuit of claim 23, wherein said load elements of said first and second sides are mutually cross-coupled transistors.

27. The integrated circuit of claim 23, wherein said offset transistor of said matrix side is substantially twice as wide as said offset transistor of said reference side.

28. The integrated circuit of claim 23, wherein said offset transistor of said reference side is substantially twice as wide as said offset transistor of said matrix side.

29. The integrated circuit of claim 23, wherein said current source consists essentially of a transistor which is matched to said transistors of said matrix cells, and which has a respective gate thereof connected to a positive power supply node.

30. The integrated circuit of claim 23, wherein said memory cells each comprise EEPROM (electrically erasable programmable read-only memory) cells.

31. The integrated circuit of claim 23, wherein said memory cells each comprise EPROM (erasable programmable read-only memory) cells.

32. An integrated circuit memory, comprising:

a matrix of memory cells, each comprising a variable-threshold transistor which is connected to be accessed by a row line and which, when turned ON, conducts current from a respective matrix bit line to ground;

a reference bit line, and a plurality of reference cells each comprising a variable-threshold transistor which is programmed to a known state, and which is connected, in common with cells of said matrix, to be accessed by a respective row line;

a sense amplifier comprising a matrix side connectable to a selected one of said matrix bit lines, and a reference side connectable to said reference bit line, each said side including;

an input node connectable to said respective bit line;

an amplifier having its input connected to said input node;

a field-effect offset transistor connected to sink a controlled current to said input node;

said offset transistors of said first and second sides having respective sizes which are unequal;

a field-effect pass transistor connected between said input node and an output node, and connected to be driven by said amplifier; and

a load element, connected to source a controlled current to said output node;

a current source connected to supply a controlled current to both said offset transistors;

equalization logic connected to conditionally equalize the potentials of said output nodes of both said sides; and

a differential amplifier connected to receive said output nodes of said first and second sides of said sense amplifier, and configured to provide a corresponding output signal.

33. The integrated circuit of claim 32, further comprising selection logic configured to connect said sense amplifier to only a selected one of said matrix bit lines.

34. The integrated circuit of claim 32, wherein said equalization logic comprises a first equalization transistor connected to equalize said output nodes, and a second transistor connected to equalize the gate potentials of said pass transistors.

35. The integrated circuit of claim 32, wherein said load elements of said first and second sides are mutually cross-coupled transistors.

36. The integrated circuit of claim 32, wherein said offset transistor of said matrix side is substantially twice as wide as said offset transistor of said reference side.

37. The integrated circuit of claim 32, wherein said offset transistor of said reference side is substantially twice as wide as said offset transistor of said matrix side.

38. The integrated circuit of claim 32, further comprising a current source connected to provided a substantially predetermined total current from said second power supply node to said first and second offset transistors in parallel.

39. The integrated circuit of claim 32, wherein said memory cells each comprise EEPROM (electrically erasable programmable read-only memory) cells.

40. The integrated circuit of claim 32, wherein said memory cells each comprise EPROM (erasable programmable read-only memory) cells.