System for halting synchronous digital modules

• US 5,355,468 A
• Filed: 04/06/1992
• Issued: 10/11/1994
• Est. Priority Date: 04/06/1992
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Whittaker, Bruce E., Jeppesen, James H. III
• Primary Examiner(s): Shaw, Dale M.
• Assistant Examiner(s): FALLER, FRAN
• Application Number:
  US07/864,111
• Time in Patent Office: 918 Days
• Field of Search: 395/550, 364/749, 364/269, 364/271.2
• US Class Current: 714/34
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 2201/86 Event-based monitoring

Abstract

In a system of multiple digital modules which is operated synchronously via common clock means, there is provided circuitry for halting each module at the same simultaneously clock-moment after sensing of a selected condition in any one of the digital modules.

Claims

1. In a system of interconnected multiple digital modules synchronously clocked from a common system clock means, a method for halting each digital module at the same clock moment comprising the steps of:

(a) sensing, in each digital module, any selected conditions or errors;

(b) generating a "freeze" signal to a maintenance control unit upon sensing said selected condition or error;

(c) transmitting HOLD signals to each said digital module from said maintenance control unit;

(d) generating, via said maintenance control unit, a momentary disabling signal to said common system clock means to obviate one clock pulse permitting all setup and transmission delay times to run out so that said HOLD signals will halt each digital module on the next rising clock pulse just after the obviated pulse, wherein the halt functions to suspend all logical conditions in each digital module at the same moment in time.

2. In a system of intercommunicating digital modules, a system for halting each module simultaneously comprising:

(a) a plurality of digital modules operating synchronously from a common clock means, each said module including;

(a1) event control logic means for sensing any error condition or shutdown condition required in the module and including;

(a2) means to generate a freeze signal to a system maintenance control means when an error or shutdown condition is detected;

(b) said maintenance control means for receiving said freeze signal from any one of said event control logic means and including;

(b2) means to transmit a hold signal to each of said digital modules;

(b2) means to activate a delay circuit which will transmit a disable signal, for one clock period, to a flip-flop means;

(b3) means to simultaneously suspend operation of the circuitry in each said digital module on the rise of the next clock following said deleted clock, said suspended operation thus maintaining all logic conditions at the moment of suspension;

(c) said flip-flop means for receiving said one-clock disable signal and deleting the transmission of one clock signal after occurrence of said freeze and hold signals;

(d) said common clock means for generating normal clock pulses for synchronous operation of each digital module.

3. The system of claim 2 wherein said common clock means generates said normal clock pulses at a rate of "K" MHZ, and further includes:

(i) auxiliary maintenance clock generation means for synchronizing a multiplicity of flip-flops in said flip-flop means.

4. The system of claim 3 wherein said auxiliary maintenance clock generation means operates at a rate of 4K MHZ or greater.

5. The system of claim 2 wherein said event control logic means includes:

(a) gating means for receiving a plurality of sense signals within said digital module, and for generating a Freeze signal upon activation of any one of said sense signals.

6. The system of claim 5 wherein said event control logic means further includes:

(a) counter means, preset by said system maintenance controller means, and connected to said gating means, for simultaneously halting said plurality of digital modules upon counting said present number of sense signals, said simultaneous halting functioning to suspend the state of all logical circuitry in each of said digital modules.

7. In a system of interconnected multiple digital modules synchronously clocked from a common system clock means, a network for suspending the logical states of circuitry in each digital module simultaneously at the same moment in time, said network comprising:

(a) a plurality of digital modules operating synchronously from a common clock means, each said digital module including;

(a1) event control logic means for sensing any error or shutdown condition in said digital module;

(a2) means to transmit a freeze signal to a system maintenance control means when an error or shutdown condition is sensed;

(b) means to distribute a common clock signal to each of said digital modules;

(c) said system maintenance control means including;

(c1) means, upon receipt of said freeze signal, to disable said means to distribute for one clock period to delete one clock signal period;

(c2) means, upon receipt of said freeze signal, to transmit a Hold signal to each said digital module;

(c3) means to simultaneously suspend the state of logic circuitry in each digital module at the moment of the rising pulse of the clock signal occurring after said deleted clock signal period;

(d) said common clock means for generating a common clock signal to each of said digital modules via said means to distribute a common clock signal.