Semiconductor memory device

• US 5,357,468 A
• Filed: 05/18/1993
• Issued: 10/18/1994
• Est. Priority Date: 05/19/1992
• Status: Expired due to Term

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Matsushita, Yuichi, Satani, Norihiko, Mitoma, Tetsuya, Cho, Shizuo
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Nguyen, Tan
• Application Number:
  US08/063,208
• Time in Patent Office: 518 Days
• Field of Search: 365/189.01, 365/189.07, 365/193, 365/194, 365/203, 365/204, 365/205, 365/207
• US Class Current: 365/189.07
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

Abstract

A semiconductor memory device according to the present invention comprises a first and second nodes, a first power supply for supplying a supply power potential to the first node, a memory cell for storing data therein; a bit line connected to the memory cell, a sense amplifier connected to the second node, for amplifying a potential of the bit line; a switching circuit connected between the first and second nodes, for coupling the first node with second node in response to a first control signal and substantial disconnecting the first node from the second node in response to a second control signal, a detecting circuit for detecting a potential of the second node and outputting a detection signal when the potential of second node is substantialy equal to the supply power potential, a control circuit applied an address signal having a first or second logic level thereto, for outputting the first control signal in response to the address signal being the first logic level and outputting the second control signal in response to the detection signal after the address signal being the second logic level.

Claims

1. A semiconductor memory device comprising:

a first node connected to receive a first power supply potential from a first power supply;

a memory cell for storing data therein;

a bit line connected to the memory cell;

a sense amplifier connected to a second node and coupled to the bit line, for amplifying a potential of the bit line;

a switching circuit connected between the first and second nodes, for coupling the first node with second node in response to a first control signal and substantially disconnecting the first node from the second node in response to a second control signal;

a detecting circuit for detecting a potential of the second node and outputting a detection signal when the potential of said second node is substantially equal to the power supply potential;

a control circuit having a first input coupled to receive said detection signal and a second input coupled to receive an address signal having a first or second logic level, the control circuit being effective for outputting the first control signal in response to the address signal changing to the first logic level and outputting the second control signal in response to the detection signal after the address signal returns to the second logic level.

2. The semiconductor memory device according to claim 1, further comprising:

a third node connected to the sense amplifier;

a fourth node connected to a second power supply for supplying a second power potential thereto;

a second switching circuit connected between the third and fourth nodes, for coupling the third node with fourth node in response to the first control signal and substantially disconnecting the third node from the fourth node in response to the second control signal.

3. A semiconductor memory device comprising:

a first node connected to receive a first power supply potential from a first power supply;

a memory cell for storing data therein;

a bit line connected to the memory cell;

a sense amplifier connected to a second node and coupled to the bit line, for amplifying a potential of the bit line;

a switching circuit connected between the first and second nodes, the switching circuit being turned on in response to a first control signal and being turned off in response to a second control signal;

a detecting circuit for detecting a potential of the second node and outputting a detection signal when the potential of second node is substantially equal to the supply power potential;

a control circuit having one input for receiving an address signal having a first or second logic level and another input for receiving said detection signal, the control circuit being effective for outputting the first control signal in response to the address signal entering the first logic level and outputting the second control signal in response to the detection signal after the address signal returns to the second logic level.

4. The semiconductor memory device according to claim 3, further comprising:

a third node connected to the sense amplifier;

a fourth node connected to a second power supply for supplying a second power potential thereto;

a second switching circuit connected between the third and fourth nodes and being turned on in response to a first control signal and turned off in response to a second control signal.

5. A semiconductor memory device comprising:

a first node connected to receive a first power supply potential from a first power supply;

a memory cell for storing data therein;

a bit line connected to the memory cell;

a sense amplifier connected to a second node and coupled to the bit line, for amplifying a potential of the bit line;

a switching circuit connected between the first and second nodes;

a detecting circuit for detecting a potential of the second node and outputting a detection signal when the potential of second node is substantially equal to the power supply potential;

a control circuit having one input for receiving an address signal having a first or second logic level and having another input for receiving the detection signal, the control circuit being effective for causing the switching circuit to be conductive when the address signal is in the first logic level and causing the switching circuit to be substantially nonconductive in response to the detection signal after the address signal has returned to the second logic level.

6. The semiconductor memory device according to claim 5, wherein the switching circuit comprises a transistor having a source electrode, a drain electrode and a gate electrode,

the source electrode being connected to the first node,

the drain electrode being connected to the second node, and

the gate electrode being connected to the control circuit.

7. A semiconductor memory comprising:

a first node connected to receive a first potential from a first power supply;

a second node connected to receive a second potential less than the first potential from a second power supply;

first and second bit lines;

a memory cell connected to the first bit line, for storing data therein;

a sense amplifier having third and fourth nodes and being coupled to said first and second bit lines for amplifying the voltage difference therebetween;

a first switching circuit for connecting the first node with the third node in response to a first control signal and substantially disconnecting the first node from the third node in response to a second control signal;

a second switching circuit for connecting the second node with the fourth node in response to the first control signal and substantially disconnecting the second node from the fourth node in response to the second control signal;

a detecting circuit for detecting a potential of the third node and outputting a detection signal at the time of the potential of the third node being substantially equal to the first potential;

a control circuit having one input connected to receive the detection signal and another input connected to receive an address signal having a first or second logic level, the control circuit being effective for outputting the first control signal in response to the address signal having the first logic level, and outputting the second control signal in response to the detection signal after the address signal returns to the second logic level.