Apparatus and method for sensitive circuit protection with set-scan testing

• US 5,357,572 A
• Filed: 09/22/1992
• Issued: 10/18/1994
• Est. Priority Date: 09/22/1992
• Status: Expired due to Term

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: Knobbe, David J., Baukus, James P., Kramer, Allan R., Bianco, Mark E., Dwyer, Douglas A., Ozdemir, Faik S.
• Primary Examiner(s): CANGIALOSI, SALVATORE A
• Application Number:
  US07/949,281
• Time in Patent Office: 756 Days
• Field of Search: 380/23, 380/3, 324/158 R, 371/22.3, 371/22.6, 371/22.5
• US Class Current: 713/193
• CPC Class Codes: G01R 31/31719 Security aspects, e.g. preventing unauthorised access during test
• CPC Class Codes: G01R 31/318558 Addressing or selecting of subparts of the device under test
• CPC Class Codes: G01R 31/318561 Identification of the subpart

Abstract

A set/scan test capability is provided for a circuit that includes sensitive subcircuits, but that can be latched out to prevent reverse engineering the sensitive elements. A mechanism to inhibit set/scan test access to at least some of the sensitive subcircuits is selectively actuated by a control circuit to override a normal set/scan test and inhibit set/scan access to the sensitive subcircuits. Various implementations are possible, such as fusible-link PROMs for irreversibly inhibiting set/scan access to the sensitive subcircuits after an initial non-inhibited test period, the use of encryption codes to enable repeated set/scan access to the sensitive subcircuits, and an erasable/reprogrammable mechanism for inhibiting set/scan access to programmed sets of subcircuits.

Claims

1. An electrical circuit having a plurality of subcircuits and a set-scan test input for testing said subcircuits in a set/scan test mode, some of said subcircuits being sensitive subcircuits protected from reverse engineering, wherein the improvement comprises:

selectable means, coupled to at least some of said sensitive circuits, for inhibiting set/scan test access to said at least some of said sensitive subcircuits, and

means for actuating said selectable means, coupled between said subcircuits and said selectable means, to inhibit set/scan access to said sensitive subcircuits while permitting set/scan access to the other subcircuits.

2. The electrical circuit of claim 1, wherein said actuating means includes means for responding to an applied control signal to actuate said selectable means.

3. The electrical circuit of claim 2, wherein said actuating means includes means further includes means for irreversibly actuating, in response to an applied control signal, said selectable means from an initially non-actuated state.

4. The electrical circuit of claim 2, wherein said actuating means includes means for responding to the application of a predetermined access code to de-actuate said set/scan inhibiting means after it has been actuated.

5. The electrical circuit of claim 4, wherein said actuating means includes means for storing an access code reference, means for decrypting an applied encrypted access code, and means, coupled between said storing means and said decrypting means, for comparing the decrypted code with said reference code to deactuate said selectable means in response to the compared codes matching.

6. The electrical circuit of claim 2, wherein said actuating means includes means for programming, coupled between the applied control signal and the sensitive subcircuits, the sensitive subcircuits for which set/scan access in inhibited.

7. The electrical circuit of claim 6, wherein said programming means comprises erasable and reprogrammable means for erasably and reprogrammably programming which of the sensitive subcircuits is to be set/scan inhibited.

8. The electrical circuit of claim 1, said actuating means including a common line for transmitting an actuating signal to a selectable means for said sensitive subcircuits.

9. The electrical circuit of claim 8, said actuating means including means for latching said set/scan inhibit means in an actuated state.

10. The electrical circuit of claim 9, wherein separate latching means are distributed to the set/scan inhibit means for each of said sensitive subcircuits.

11. The electrical circuit of claim 8, further comprising means for clocking a set/scan test signal among said subcircuits, and means for applying an actuating signal to said common line in synchronism with the clocking of said set/scan test signal to actuate the set/scan inhibit means for desired sensitive subcircuits when said set/scan test signal is present at said subcircuits.

12. The electrical circuit of claim 1, said selectable means including means for inhibiting set/scan access to each of said sensitive subcircuits, and said actuating means includes programmable means for actuating the set/scan inhibit means only for programmed sensitive subcircuits.

13. The electrical circuit of claim 12, wherein said means for inhibiting set/scan access to said sensitive subcircuits comprises respective bypass circuits bypassing said sensitive subcircuits, and means for diverting a set/scan test signal away from said subcircuits to their respective bypass circuits.

14. An electrical circuit having a plurality of interconnected subcircuits, some of which are sensitive subcircuits protected from reverse engineering, a set/scan test input for testing said subcircuits in a set/scan test mode, respective bypass circuits for bypassing said subcircuits, respective switches for steering a set/scan test signal between a subcircuit and the bypass circuit for said subcircuit, and a set/scan control means for controlling the operation of said switches during a normal set/scan test, wherein the improvement comprises

access control means coupled between the set/scan control means and the switches for said sensitive subcircuits to control the operation of said switches and thereby the access of set/scan test signals to said sensitive subcircuits, and

selectable means, coupled to said access control means, for operating said access control means to convert said control means from an initial state enabling the access of set/scan signals to said sensitive subcircuits, to a secure state in which said access control means operates the switches for said sensitive subcircuits to override said set/scan control means and inhibit the access of set/scan test signals to at least some of said sensitive subcircuits.

15. The electrical circuit of claim 14, said access control means including means for irreversibly converting from said initial state to said secure state.

16. The electrical circuit of claim 15, said access control means comprising a fusible link PROM (programmable read only memory) cell, and said selectable access control operating means comprising a programming cell connected to program said fusible link PROM.

17. The electrical circuit of claim 14, said selectable access control operating means including means for decrypting an applied encrypted access code, and said access control means comprising means for comparing the decrypted code with a reference code and, in response to the compared codes matching, converting from said secure state to an enabling state in which set/scan access to said sensitive subcircuits is enabled.

18. The electrical circuit of claim 14, further comprising a common sensitive transmission line coupled between the switches and said sensitive subcircuits, said access control means comprising means for responding to the joint pressure of set/scan enable signals from said set/scan control means and from said selectable access control operating means to provide set/scan enable switch signals along said common sensitive transmission line to the switches for said sensitive subcircuits.

19. The electrical circuit of claim 18, further comprising a common non-sensitive transmission line coupled between the switches and said non-sensitive subcircuits, said set/scan control means comprising means for providing set/scan enable switch signals along said common non-sensitive transmission line to the switches for each of the non-sensitive circuits.

20. The electrical circuits of claim 14, further comprising a sensitive transmission line for each of the switches and said sensitive subcircuits, said access control means comprising means for responding to the joint pressure of set/scan enable signals from said set/scan control means and from said selectable access control operating means to provide set/scan enable switch signals along said respective transmission lines to the switches for said sensitive subcircuits.

21. The electrical circuit of claim 14, said access control means comprising means responsive to an enable signal from said selectable access control operating means for converting from said secure state to an enabling state in which set/scan access to said sensitive subcircuits is enabled.

22. The electrical circuit of claim 21, said access control means comprising an erasable PROM (programmable read only memory) cell storing the addresses of said sensitive subcircuits.

23. A method of protecting an electric circuit that includes sensitive subcircuits protected from reverse engineering and a set/scan test capability from reverse engineering said sensitive subcircuits using the set/scan test capability, comprising the steps of:

initially providing a set/scan test access to said sensitive subcircuits in said circuit; and

thereafter inhibiting set/scan test access to said sensitive subcircuits.

24. The method of claim 23, further comprising the step of performing a set/scan test of said circuit, including said sensitive subcircuits, prior to inhibiting set/scan test access to said sensitive subcircuits.

25. The method of claim 24, wherein said step of set/scan test access to said sensitive subcircuits includes irreversibly inhibiting set/scan test access to said sensitive subcircuits.

26. The method of claim 24, wherein said step of inhibiting set/scan test access to said sensitive subcircuits includes reversibly inhibiting set/scan access to said sensitive subcircuits and, further comprising the steps of removing said set/scan inhibition, performing a set/scan test of said circuit including said sensitive subcircuits, and thereafter reinstating said set/scan inhibition for said sensitive subcircuits.

27. The method of claim 26, wherein said set/scan inhibition is removed by storing an access code in said circuit, applying an access code to said circuit, and removing said inhibition in response to said stored and applied access codes matching.