Graphics processor with enhanced memory control circuitry for use in a video game system or the like

• US 5,357,604 A
• Filed: 04/08/1994
• Issued: 10/18/1994
• Est. Priority Date: 01/30/1992
• Status: Expired due to Term

• Current Assignee: Nintendo Company Limited
• Original Assignee: N To B Ltd.
• Inventors: Graham, Carl N., Cheese, Ben, Warnes, Peter R., San, Jeremy E.
• Primary Examiner(s): RICHARDSON, ROBERT
• Application Number:
  US08/224,411
• Time in Patent Office: 193 Days
• Field of Search: 395/162, 395/163, 395/164, 395/425, 273/433, 273/434, 273/435, 345/189, 345/190, 345/24, 345/27
• US Class Current: 463/31
• CPC Class Codes: G06T 17/00 Three dimensional [3D] modelling, e.g. data description of 3D objects

Abstract

A fully programmable, graphics microprocessor is embodied in a removable external memory unit for connection with a host information processing system. In an exemplary embodiment, a video game system is described including a host video game system and a pluggable video game cartridge housing the graphics microprocessor. The game cartridge also includes a read-only program memory (ROM) and a random-access memory (RAM). The graphics coprocessor operates in conjunction with a three bus architecture embodied on the game cartridge. The graphics processor using this bus architecture may execute programs from either the program ROM, external RAM or its own internal cache RAM. The fully user programmable graphics coprocessor has an instruction set which is designed to efficiently implement arithmetic operations associated with 3-D graphics and, for example, includes special instructions executed by dedicated hardware for plotting individual pixels in the host video game system'"'"'s character mapped display which, from the programmer'"'"'s point of view, creates a "virtual" bit map by permitting the addressing of individual pixels--even though the host system is character based. The graphics coprocessor interacts with the host coprocessor such that the graphics coprocessor'"'"'s 16 general registers are accessible to the host processor at all times.

Claims

1. In a video game system having a main console including a game microprocessor for executing a video game program stored in an external memory system and a picture processing unit coupled to said game microprocessor and a video random access memory, coupled to said picture processing unit, for storing data for use in generating a video display, said video game external memory system comprising:

a cartridge for removable connection to said main console, said cartridge providing a housing for at least;

a program memory for storing said video game program;

an additional memory for storing at least video graphics data; and

a graphics processor, coupled to said program memory, and said additional memory, and coupled to said game microprocessor when said cartridge is connected to said main console for executing at least part of said video game program, said external memory system including a program memory controller for controlling access to said program memory and an additional memory controller for controlling access to said additional memory.

2. A video game external memory system according to claim 1, wherein said graphics processor includes a cache memory and cache control means for loading instructions stored in said program memory into said cache memory, wherein said cache memory is said additional memory and said cache control means is said additional memory controller.

3. A video game external memory system according to claim 2, wherein said cache control means includes means for loading said cache memory with instructions in response to a predetermined instruction stored in said program memory.

4. A video game external memory system according to claim 2, wherein said cache control means includes a cache base register for storing the starting program memory location which has been loaded into the cache memory.

5. A video game external memory system according to claim 4, wherein said graphics processor includes decoding means for decoding a cache load instruction and means for loading said cache base register in response to the decoding of said cache load instruction.

6. A video game external memory system according to claim 2, wherein said graphics processor includes a program counter and further including bus means for coupling the contents of the program counter to said cache control means.

7. A video game external memory system according to claim 2, wherein said cache control means includes cache tag bit register means for indicating whether program instructions are resident in the cache memory.

8. A video game external memory system according to claim 2, further including an instruction bus, wherein said cache memory includes at least one output coupled to said instruction bus.

9. A video game external memory system according to claim 2, further including at least one source data bus, and a program counter bus, said cache control means being coupled to each of said buses.

10. A video game external memory system according to claim 2, wherein said cache control means includes means for loading at least some instructions into said cache memory when said at least some instructions are being executed from said program memory.

11. A video game external memory system according to claim 1, further including a cache memory, said program memory controller including means for loading said cache memory with program instructions.

12. A video game external memory system according to claim 1, wherein said graphics processor is coupled to a program memory address bus and said program memory controller includes a multiplexer for selecting an address to place on said program memory address bus.

13. A video game external memory system according to claim 12, wherein said multiplexer is coupled, in use, to receive a game microprocessor generated address.

14. A video game external memory system according to claim 1, wherein said program memory controller includes means for receiving program memory address information from said game microprocessor for identifying program instructions for said graphics processor to execute.

15. A video game external memory system according to claim 1, further including a plurality of registers, wherein said program memory controller includes means for automatically initiating a program memory data fetch in response to one of said plurality of registers being accessed.

16. A programmable graphics processor, for use with a host information processing system having an address bus and a data bus and having a program memory for storing a videographics program, said programmable graphics processor comprising:

a host interface bus coupled to at least one of said address bus and said data bus;

a cache memory, coupled to said host interface bus, for storing at least some of the instructions of said videographics program;

means for executing instructions stored in said cache memory and said program memory; and

cache control means for loading instructions from said program memory into said cache memory.

17. A programmable graphics processor according to claim 16, wherein said cache control means includes means for loading said cache memory with instructions in response to a predetermined instruction stored in said program memory.

18. A programmable graphics processor according to claim 16, wherein said information processing system includes a random access memory unit (RAM) and wherein said cache control means includes means for receiving instructions from said RAM.

19. A programmable graphics processor according to claim 16, wherein said cache control means includes a cache base register for storing the starting program memory location which has been loaded into the cache memory.

20. A programmable graphics processor according to claim 19, further including decoding means for decoding a cache load instruction and means for loading said cache base register in response to the decoding of said cache load instruction.

21. A programmable graphics processor according to claim 16, wherein said graphics processor includes a program counter and further including bus means for coupling the contents of the program counter to said cache control means.

22. A programmable graphics processor according to claim 16, wherein said cache control means includes cache tag bit register means for indicating whether program instructions are resident in the cache memory.

23. A programmable graphics processor according to claim 16, further including an instruction bus, wherein said cache memory includes at least one output coupled to said instruction bus.

24. A programmable graphics processor according to claim 16, further including at least one source data bus, and a program counter bus, said cache control means being coupled to each of said buses.

25. A programmable graphics processor according to claim 16, wherein said cache control means includes means for loading at least some instructions into said cache memory when said at least some instructions are being executed from said program memory.

26. A programmable graphics processor according to claim 16, wherein said cache control means controls loading of the cache in predetermined multi-byte segments, and wherein said graphics processor includes means for detecting when a branch instruction stored in said program memory is to be executed, and branch instruction control means for completing the loading of a predetermined multi-byte segment in response to said means for detecting.

27. A programmable graphics processor according to claim 16, wherein said cache control means includes out-of-range means for indicating whether an instruction to be executed is out of the current range of the cache memory.

28. A programmable graphics processor according to claim 27, further including tag register means for indicating that a predetermined instruction is stored in the cache, said tag register means including a tag register and means for setting at least one tag in said tag register if said out-of-range means indicates that the predetermined instruction is not out of range.

29. A programmable graphics processor according to claim 16, wherein said cache control means includes means for initiating a program memory fetch in response to determining that an instruction is not present in the cache memory.

30. A programmable graphics processor according claim 16, further including a program counter which identifies the address of the instruction to be executed, and wherein said cache control means includes a cache base register for receiving at least part of the contents of said program counter, a cache range detector, coupled to receive a least part of the contents of said program counter and coupled to said cache base register for generating an indication as to whether an instruction to be executed is in the cache memory.

31. A programmable graphics processor according to claim 30, wherein said cache range detector includes means for generating at least part of a cache memory address.

32. A programmable graphics processor according to claim 26, wherein said cache control means includes tag register means for storing a plurality of indications of whether instructions are stored in said cache memory, means responsive to the output of said range detector for setting one of said plurality of indications.

33. A graphics processor for use with a host processing system having a host address bus and host data bus and a program memory for storing a videographics program, said graphics processor comprising:

an arithmetic and logic unit for executing instructions stored in said program memory;

a host interface bus coupled to at least one of said host address bus and said host data bus; and

a program memory controller coupled to said host interface bus for controlling access to said program memory and for selectively enabling at least one of said host processing system and said graphics processor to access said program memory.

34. A graphics processor according to claim 33, further including a cache memory, said program memory controller including means for loading said cache memory with program instructions.

35. A graphics processor according to claim 34, wherein said means for loading said cache memory includes means, responsive to the decoding of a branch instruction, for completing a cache loading operation prior to executing said branch operation.

36. A graphics processor according to claim 33, wherein said program memory includes data pins and a data bus coupled to said data pins, wherein said graphic processor is coupled to said data bus and said program memory controller includes timing means for indicating when data is available at the program memory data pins.

37. A graphics processor according to claim 33, wherein said graphics processor is coupled to a program memory address bus and said program memory controller includes a multiplexer for selecting an address to place on said program memory address bus.

38. A graphics processor according to claim 37, wherein said multiplexer is coupled, in use, to receive a host processing system generated address.

39. A graphics processor according to claim 33, wherein said program memory controller includes means for receiving program memory address information via said host interface bus from said host processing system for identifying program instructions for said graphics processor to execute.

40. A graphics processor according to claim 33, further including a plurality of registers, wherein said program memory controller includes means for automatically initiating a program memory data fetch in response to one of said plurality of registers being accessed.

41. A graphics processor according to claim 40, wherein the contents of said one of said plurality of registers stores the address of the program memory location storing data to be fetched.

42. A graphics processor according to claim 33, wherein said program memory includes a plurality of data pins and said program memory controller includes means for receiving data from said plurality of data pins.

43. A graphic processor according to claim 42, further including a plurality of registers, and at least one bus coupled to said plurality of registers, wherein said means for receiving includes buffer register means and means for coupling the contents of said buffer register means to said at least one bus.

44. A graphics processor according to claim 33, wherein said graphics processor is coupled to a random access memory (RAM) and further includes a RAM controller for controlling access to said RAM.

45. A graphics processor for use with a host processing system having a host address bus and a host data bus, a program memory for storing a videographics program, and a random access memory (RAM), said graphics processor comprising:

a host interface bus coupled to at least one of said host address bus and host data bus;

means, coupled to said host interface bus, for receiving a RAM address from said host processing system;

graphics processing means for generating RAM addresses; and

a RAM controller for selecting between a host processing system RAM address and a graphics processing means generated RAM address and for coupling same to said RAM.

46. A graphics processor according to claim 45, further including at least one bus, wherein said RAM controller includes means for receiving data from said RAM and for coupling said data to at least one bus.

47. A graphics processor according to claim 45, wherein said RAM controller includes buffer means for temporarily storing data to be written to RAM.

48. A graphics processor according to claim 45, further including at least one status register wherein said RAM controller includes multiplexer means for receiving a host processing system generated address and a graphics processing means generated address, and for coupling one of said addresses to said RAM depending upon the state of at least one status bit stored in said status register.

49. A graphics processor according to claim 45, wherein said RAM controller includes arbitration logic for determining the priority of received RAM access requests.

50. A graphics processor according to claim 49, wherein said graphics processing means includes means for executing instructions and wherein said arbitration logic is enabled only when said graphics processing means is enabled to execute instruction.

51. A graphics processor according to claim 49, wherein said graphics processing means includes means for generating a plurality of requests for RAM access, and wherein said arbitration logic includes means for prioritizing said plurality of requests.

52. In an information processing apparatus having a main processing unit including a first processing device for executing a first portion of a program stored in an external memory system, a removable external memory system comprising:

a cartridge removably connectable to said main processing unit, providing said cartridge a housing for at least;

a program memory for storing said first portion of said program and a second portion of said program; and

an external processing unit, coupled to said program memory, for executing said second portion of said program, said processing unit including a cache memory for receiving at least some instructions of said second portion of said program from said program memory.

53. An external memory system according to claim 52, wherein said external processing unit includes means for executing an instruction for initiating the loading of instructions into said cache memory.

54. An external memory system according to claim 52, further including an instruction bus, wherein said cache memory is coupled to said instruction bus for loading instructions stored therein onto said instruction bus.

55. An external memory system according to claim 52, wherein said cache memory is coupled to cache memory control circuitry for identifying whether an instruction resides in the cache memory.

56. In an information processing system having a host processing unit for executing a program stored in an external memory system, said external memory system, comprising:

a program memory for storing said program,

a plurality of registers; and

a remote processor for executing instructions stored in said program memory, including means for automatically initiating data fetches from said program memory in response to one of said plurality of registers being accessed, said remote processor being operable to execute at least one instruction while said data fetch is taking place.

57. In an information processing system having a host processing system, an external memory system removably coupled to said host system, said external memory system comprising:

a cartridge removably connected to said host processing system for housing at least;

a program memory;

an additional memory; and

a graphics processor coupled to said program memory and said additional memory;

said graphics processor including;

a program memory controller for controlling access to said program memory; and

an additional memory controller for controlling access to said additional memory.

58. An eternal memory system according to claim 57, wherein said additional controller includes means for determining priority between a plurality of received requests for access to said additional memory.

59. An external memory system according to claim 58, further including plotting circuitry, and wherein said additional memory controller receives a plot request signal indicating that a memory access is required for a plotting operation being performed.