Low power digital signal buffer circuit

• US 5,359,240 A
• Filed: 01/25/1993
• Issued: 10/25/1994
• Est. Priority Date: 01/25/1993
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Sandhu, Bal S.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): Sanders, Andrew
• Application Number:
  US08/008,165
• Time in Patent Office: 638 Days
• Field of Search: 307/451, 307/475, 307/443
• US Class Current: 326/83
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A low power signal buffer circuit for TTL signals includes a voltage reference controlled complementary MOSFET ("C-MOSFET") amplifier and a C-MOSFET inverter. The voltage reference controlled C-MOSFET amplifier receives a fixed reference voltage and a TTL input signal and provides a reference bias voltage. The C-MOSFET inverter has a pull-up P-type MOSFET which receives and is biased by the reference bias voltage, and a pull-down N-type MOSFET which receives the TTL input signal. The C-MOSFET inverter provides a TTL output signal with a substantially increased dynamic signal amplitude range. Current drain from the DC power supply for the buffer circuit decreases significantly as the TTL input signal state changes from "low" to "high" (e.g. logical "zero" to logical "one").

Claims

1. A low power signal buffer circuit, comprising:

input signal inverter means for receiving an active reference signal and a digital input signal, and for inverting said received digital input signal in accordance with said received active reference signal to provide a digital output signal; and

active reference signal generator means coupled to said input signal inverter means for receiving at least one fixed reference voltage and said digital input signal and in accordance therewith providing said active reference signal;

wherein said input signal inverter means and active reference signal generator means receive a dc supply current which includes first and second current levels, said received digital input signal includes low and high logic levels, said first and second current levels are received when said low and high logic levels are received, respectively, and said second current level is substantially less than said first current level.

2. A low power signal buffer circuit as recited in claim 1, wherein said input signal inverter means comprises a pull-up MOSFET and a pull-down MOSFET which are mutually coupled, and wherein said pull-up MOSFET receives said active reference signal.

3. A low power signal buffer circuit as recited in claim 1, wherein said active reference signal generator means comprises mutually coupled first and second MOSFETs, and wherein said first MOSFET receives said at least one fixed reference voltage and said digital input signal.

4. A low power MOSFET buffer circuit comprising:

a pull-up MOSFET which includes a reference bias input terminal for receiving a reference bias voltage, and further includes a pull-up MOSFET output terminal;

a pull-down MOSFET which includes an input signal terminal for receiving a TTL input signal, and further includes a pull-down MOSFET output terminal coupled to said pull-up MOSFET output terminal for providing a TTL output signal in accordance with said received reference bias voltage and said received TTL input signal; and

reference bias voltage generator means coupled to said pull-up MOSFET for receiving at least one fixed reference voltage and said TTL input signal and in accordance therewith providing said reference bias voltage;

wherein said pull-up MOSFET and reference bias voltage generator means receive a dc supply current which includes first and second current levels, said received TTL input signal includes low and high TTL logic levels, said first and second current levels are received when said low and high TTL logic levels are received, respectively, and said second current level is substantially less than said first current level.

5. A low power signal buffer circuit as recited in claim 4, wherein said reference bias voltage generator means comprises mutually coupled first and second MOSFETs, and wherein said first MOSFET receives said at least one fixed reference voltage and said TTL input signal.

6. A low power signal buffer circuit, comprising:

input signal inverter means for receiving an active reference signal and a digital input signal with a dynamic input signal amplitude range, and for inverting said received digital input signal in accordance with said received active reference signal to provide a digital output signal with a dynamic output signal amplitude range, wherein said dynamic output signal amplitude range is greater than said dynamic input signal amplitude range; and

active reference signal generator means coupled to said input signal inverter means for receiving at least one fixed reference voltage and said digital input signal and in accordance therewith providing said active reference signal;

wherein said input signal inverter means and active reference signal generator means receive a dc supply current which includes first and second current levels, said received digital input signal includes low and high logic levels, said first and second current levels are received when said low and high logic levels are received, respectively, and said second current level is substantially less than said first current level.

7. A low power signal buffer circuit as recited in claim 6, wherein said input signal inverter means comprises a pull-up MOSFET and a pull-down MOSFET which are mutually coupled, and wherein said pull-up MOSFET receives said active reference signal.

8. A low power signal buffer circuit as recited in claim 6, wherein said active reference signal generator means comprises mutually coupled first and second MOSFETs, and wherein said first MOSFET receives said at least one fixed reference voltage and said digital input signal.

9. A low power MOSFET buffer circuit comprising:

a pull-up MOSFET which includes a reference bias input terminal for receiving a reference bias voltage, and further includes a pull-up MOSFET output terminal;

a pull-down MOSFET which includes an input signal terminal for receiving a TTL input signal with a dynamic input signal amplitude range, and further includes a pull-down MOSFET output terminal coupled to said pull-up MOSFET output terminal for providing a TTL output signal with a dynamic output signal amplitude range in accordance with said received reference bias voltage and said received TTL input signal, wherein said dynamic output signal amplitude range is greater than said dynamic input signal amplitude range; and

reference bias voltage generator means coupled to said pull-up MOSFET for receiving at least one fixed reference voltage and said TTL input signal and in accordance therewith providing said reference bias voltage;

wherein said pull-up MOSFET and reference bias voltage generator means receive a dc supply current which includes first and second current levels, said received TTL input signal includes low and high TTL logic levels, said first and second current levels are received when said low and high TTL logic levels are received, respectively, and said second current level is substantially less than said first current level.

10. A low power MOSFET buffer circuit as recited in claim 9, wherein said reference bias voltage generator means comprises mutually coupled first and second MOSFETs, and wherein said first MOSFET receives said at least one fixed reference voltage and said TTL input signal.

11. A low power signal buffer circuit, comprising:

input signal inverter means for receiving an active reference signal and a digital input signal, and for inverting said received digital input signal in accordance with said received active reference signal to provide a digital output signal; and

active reference signal generator means coupled to said input signal inverter means for receiving at least one fixed reference voltage and said digital input signal and in accordance therewith providing said active reference signal, wherein said active reference signal generator means comprises mutually coupled first and second MOSFETs, and wherein said first MOSFET receives said at least one fixed reference voltage and said digital input signal.

12. A low power MOSFET buffer circuit comprising:

a pull-up MOSFET which includes a reference bias input terminal for receiving a reference bias voltage, and further includes a pull-up MOSFET output terminal;

a pull-down MOSFET which includes an input signal terminal for receiving a TTL input signal, and further includes a pull-down MOSFET output terminal coupled to said pull-up MOSFET output terminal for providing a TTL output signal in accordance with said received reference bias voltage and said received TTL input signal; and

reference bias voltage generator means coupled to said pull-up MOSFET for receiving at least one fixed reference voltage and said TTL input signal and in accordance therewith providing said reference bias voltage, wherein said reference bias voltage generator means comprises mutually coupled first and second MOSFETs, and wherein said first MOSFET receives said at least one fixed reference voltage and said TTL input signal.

13. A low power signal buffer circuit, comprising:

input signal inverter means for receiving an active reference signal and a digital input signal with a dynamic input signal amplitude range, and for inverting said received digital input signal in accordance with said received active reference signal to provide a digital output signal with a dynamic output signal amplitude range, wherein said dynamic output signal amplitude range is greater than said dynamic input signal amplitude range; and

active reference signal generator means coupled to said input signal inverter means for receiving at least one fixed reference voltage and said digital input signal and in accordance therewith providing said active reference signal, wherein said active reference signal generator means comprises mutually coupled first and second MOSFETs, and wherein said first MOSFET receives said at least one fixed reference voltage and said digital input signal.

14. A low power MOSFET buffer circuit comprising:

a pull-up MOSFET which includes a reference bias input terminal for receiving a reference bias voltage, and further includes a pull-up MOSFET output terminal;

a pull-down MOSFET which includes an input signal terminal for receiving a TTL input signal with a dynamic input signal amplitude range, and further includes a pull-down MOSFET output terminal coupled to said pull-up MOSFET output terminal for providing a TTL output signal with a dynamic output signal amplitude range in accordance with said received reference bias voltage and said received TTL input signal, wherein said dynamic output signal amplitude range is greater than said dynamic input signal amplitude range; and

reference bias voltage generator means coupled to said pull-up MOSFET for receiving at least one fixed reference voltage and said TTL input signal and in accordance therewith providing said reference bias voltage, wherein said reference bias voltage generator means comprises mutually coupled first and second MOSFETs, and wherein said first MOSFET receives said at least one fixed reference voltage and said TTL input signal.