Self-biased cascode current mirror having high voltage swing and low power consumption

• US 5,359,296 A
• Filed: 09/10/1993
• Issued: 10/25/1994
• Est. Priority Date: 09/10/1993
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Rybicki, Mathew A., Brooks, Todd L.
• Primary Examiner(s): MOTTOLA, STEVEN J
• Application Number:
  US08/119,940
• Time in Patent Office: 410 Days
• Field of Search: 330/277, 330/288, 330/296, 330/310, 307/296.1, 323/315, 323/316
• US Class Current: 330/288
• CPC Class Codes: G05F 3/26 Current mirrors
• CPC Class Codes: H03F 3/345 with field-effect devices H03F3/347 takes precedence

Abstract

A self-biased cascode current mirror includes a current mirror (60), and a cascode bias generator (50). The cascode bias generator (50) includes a resistor (51) to provide a bias voltage for the current mirror (60). The current mirror (60) includes cascode transistor (64) and two mirror transistors (62, 63). The bias voltage is approximately equal to a minimum saturation voltage of the cascode transistor (64) plus a gate-source voltage of the transistor (63) of the current mirror (60). The self-biased cascode current mirror (60) has a high output impedance and high voltage swing while providing low power consumption and requiring a small layout area.

Claims

1. A self-biased cascode current mirror circuit, comprising:

a resistive element having a first terminal for providing a bias voltage in response to receiving an input current, and a second terminal;

a first transistor having a first current electrode coupled to the second terminal of the resistive element, a control electrode coupled to the first terminal of the resistor for receiving the bias voltage, and a second current electrode;

a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the first current electrode of the first transistor, and a second current electrode coupled to a power supply voltage terminal;

a third transistor having a first current electrode for providing an output current, a control electrode for receiving the bias voltage, and a second current electrode; and

a fourth transistor having a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to the first current electrode of the first transistor, and a second current electrode coupled to the power supply voltage terminal.

2. The current mirror circuit of claim 1, wherein said first, second, third, and fourth transistors are metal oxide semiconductor field effect transistors.

3. The current mirror circuit of claim 1, wherein said first, second, third, and fourth transistors are N-channel transistors.

4. The current mirror circuit of claim 1, wherein the power supply voltage terminal is characterized as being coupled to ground potential.

5. The current mirror circuit of claim 1, further comprising a current source having a first terminal coupled to a second power supply voltage terminal, and a second terminal coupled to the first terminal of the resistor, the current source for providing the input current.

6. The current mirror circuit of claim 1, wherein the bias voltage is equal to approximately the sum of a voltage at the gate of the fourth transistor and the minimum saturation voltage of the third transistor.

7. The current mirror circuit of claim 1, wherein the resistive element is a resistor.