Memory array having a plurality of address partitions
First Claim
1. A memory array having a plurality of memory cells in which each of the memory cells in the memory array includes a first and a second control gate, such that a simultaneous energization of the first and second control gates enables the addressing of each of the memory cells, said memory array comprising:
- a plurality of sub-arrays, each of said sub-arrays includes a plurality of memory cells arranged in a matrix of rows and columns, with the first control gate of each of the memory cells in a row being electrically connected, thereby forming a plurality of X-address lines, and with the second control gate of each of the memory cells in a column being electrically connected together, thereby forming a plurality of Y-address lines;
a plurality of row address lines; and
a plurality of column address lines, said plurality of row and column address lines being operatively connected to said sub-arrays such that a simultaneous energization of a pair of address lines selected from each of said row and column address lines enables the selective addressing one of said sub-arrays;
wherein the addressing of a selected memory cell in the memory array comprises the simultaneous energization of a selected pair of said row and column address lines for the selective addressing of one of said sub-arrays, and further comprises the simultaneous energization of a selected pair of said X-address and Y-address lines for the selective addressing of said selected memory cell in said selected sub-array.
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Abstract
Non-volatile semiconductor memory integrated circuits which partition a main memory array into sub-arrays. Address lines of the main memory array are also partitioned into four groups. The first group and the second group are dedicated for the addressing of the sub-arrays. Each of the sub-arrays can be addressed by a simultaneous energization of a pair of address lines selected from the first and the second group. The third group and the fourth group are used for the addressing for individual memory cells in the sub-arrays. The simultaneous energization of a pair of address lines selected from the third and the fourth group can address any of the memory cells within a selected sub-array. The memory circuits of the present invention are applicable for memory cells with four terminals. In a first embodiment of the invention, the memory circuit is a one-bit wide circuit. In a second and a third embodiment of the invention, the memory circuits are designed as multi-bit-wide circuits whereby data can be programmed parallely. Moreover, in the third embodiment, storage register circuits are implemented, such that during programming, data are cumulatively loaded into the register circuits within a time period, and are simultaneously programmed into the main array within another time period. The programming and the cumulative data loading steps are executed concurrently, resulting in no idle time being wasted. As a consequence, programming can be as fast as reading for memory circuit of the third embodiment of the invention.
48 Citations
22 Claims
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1. A memory array having a plurality of memory cells in which each of the memory cells in the memory array includes a first and a second control gate, such that a simultaneous energization of the first and second control gates enables the addressing of each of the memory cells, said memory array comprising:
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a plurality of sub-arrays, each of said sub-arrays includes a plurality of memory cells arranged in a matrix of rows and columns, with the first control gate of each of the memory cells in a row being electrically connected, thereby forming a plurality of X-address lines, and with the second control gate of each of the memory cells in a column being electrically connected together, thereby forming a plurality of Y-address lines; a plurality of row address lines; and a plurality of column address lines, said plurality of row and column address lines being operatively connected to said sub-arrays such that a simultaneous energization of a pair of address lines selected from each of said row and column address lines enables the selective addressing one of said sub-arrays; wherein the addressing of a selected memory cell in the memory array comprises the simultaneous energization of a selected pair of said row and column address lines for the selective addressing of one of said sub-arrays, and further comprises the simultaneous energization of a selected pair of said X-address and Y-address lines for the selective addressing of said selected memory cell in said selected sub-array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A memory array including a plurality of memory sectors, each of the memory sectors having a plurality of memory cells in which each of the memory cells includes a first and a second control gate, such that a simultaneous energization of the first and second control gates enables the addressing of each of the memory cells, each of said memory sectors comprising:
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a plurality of sub-arrays, each of said sub-arrays includes a plurality of memory cells arranged in a matrix of rows and columns, with the first control gate of each of the memory cells in a row being electrically connected, thereby forming a plurality of X-address lines, and with the second control gate of each of the memory cells in a column being electrically connected together, thereby forming a plurality of Y-address lines; a plurality of row address lines; and a plurality of column address lines, said plurality of row and column address lines being operatively connected to said sub-arrays such that a simultaneous energization of a pair of address lines selected from each of said row and column address lines enables the selective addressing one of said sub-arrays; wherein said plurality of memory sectors are operatively connected together with corresponding X-address, Y-address, row address and column address lines in each of said memory sectors being electrically connected together, thereby enabling each of the memory cells in each of the sub-arrays in each of the memory sectors to be selectively addressable via a simultaneous energization of a set of address lines selected from said X-address, Y-address, row address and column address lines. - View Dependent Claims (15, 16, 17)
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18. A W-bit-wide memory circuit having W memory sectors and N address lines formed in a semiconductor substrate, each of said W memory sectors comprising:
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a plurality of sub-arrays arranged in a first matrix of P rows and Q columns, each of said sub-arrays comprising a plurality of memory cells arranged in a second matrix of R rows and S columns, wherein the mathematical sum of P, Q, R and S equals N;
N being an integer;a row addressing circuit controlled by P row address lines; a column addressing circuit controlled by Q column address lines, said row and column addressing circuits being operatively connected to said plurality of sub-arrays such that a simultaneous energization of a pair of address lines selected from each of said P row and Q column address lines enables the selective addressing of one of said sub-arrays; R X-address lines traversing each of said sub-arrays; S Y-address lines traversing each of said sub-arrays, said S Y-address lines being formed on the semiconductor substrate substantially perpendicular to said R X-address lines, such that a simultaneous energization of a pair of address lines selected from each of said R X-address and S Y-address lines enables the selective addressing of one of said memory cells in said addressed sub-array.
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19. A W-bit wide memory circuit including Q memory sectors having N address lines formed in a semiconductor substrate, each of said Q memory sectors comprising:
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a plurality of sub-arrays arranged in a first matrix of P rows and Q columns, each of said sub-arrays comprising a plurality of memory cells arranged in a second matrix of R rows and S columns, wherein the mathematical sum of P, Q, R and S equals N;
N being an integer;a row addressing circuit controlled by P row address lines; a column addressing circuit controlled by Q column address lines, said row and column addressing circuits being operatively connected to each of said Q memory sectors such that a simultaneous energization of a pair of address lines selected from each of said P row and Q column address lines enables the selective addressing of one of said sub-arrays; R X-address lines traversing each of said sub-arrays; and S Y-address lines traversing each of said sub-arrays, said S Y-address lines being formed on the semiconductor substrate substantially perpendicular to said R X-address lines, such that a simultaneous energization of a pair of address lines selected from each of said R X-address and S Y-address lines enables the selective addressing of one of said memory cells in said addressed sub-array. - View Dependent Claims (20, 21, 22)
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Specification