Circuit arrangement for adjusting the bit rates of two signals

• US 5,359,605 A
• Filed: 12/13/1993
• Issued: 10/25/1994
• Est. Priority Date: 06/22/1989
• Status: Expired due to Term

• Current Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Robledo, Miguel, Niegel, Michael, Urbansky, Ralph
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): Kizou, Hassan
• Application Number:
  US08/167,432
• Time in Patent Office: 316 Days
• Field of Search: 370/84, 370/100.1, 370/102, 370/105.1, 370/108, 370/112, 370/104.3, 370/106, 370/112, 370/84, 370/100.1, 370/102, 370/105.1, 370/105.3, 370/108, 370/112, 375/106, 375/112
• US Class Current: 370/366
• CPC Class Codes: H04J 3/076 Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking

Abstract

A circuit for adjusting the bit rates of two signals is necessary for plesiochronous multiplexers, for example, to bring the plesiochronous signals, which are to be combined to one digital signal of the next higher hierarchy, to the same bit rate. For this purpose, the circuit arrangement comprises an elastic store (4) as well as a justification decision circuit (15, 16). In order that a circuit having such features can be used for bit rates of the order of 140 Mbit/s and yet can be arranged largely in CMOS technology, the bit clocks of the first and second signals are reduced at the ratio of 1:n. Furthermore, a serial-to-parallel converter (2) converts bit groups of n serial bits of a first signal into bit groups of n parallel bits, which are written in groups into the elastic store (4) and are also read out in groups. The parallel bit groups read out are applied to a controllable selection matrix (5) having n outputs, which transmits n selected bits of more than one bit group to n outputs. The justification decision circuit (15, 16) controls the reading operation of the elastic store (4) and also the selection matrix (5).

Claims

1. A circuit for adjusting bit rates of input and output signals, which input and output signals comprise bits organized into frames, each frame having a same plurality of frame positions, which frame positions are marked by edges of corresponding input and output bit clock signals, the circuit comprising:

a) input divider means (11,14)

responsive to the input bit clock signal for supplying a reduced input bit clock signal at a reduced bit clock rate, which reduced input bit clock rate is reduced at a ratio of 1;

n with respect to a bit clock rate of the input bit clock signal, where n is an integer greater than 1, and

output divider means responsive to the output bit clock signal, for supplying a reduced output bit clock signal at a reduced output bit clock rate;

b) a serial-to-parallel converter coupled to the input divider means and responsive to the reduced input bit clock signal for converting groups of n serial bits of the input signal into groups of n parallel bits;

c) an elastic store coupled to the serial-to-parallel converter to receive the groups of n parallel bits at the reduced input bit clock rate and to supply the groups of n parallel bits at the reduced input bit clock rate;

d) a controllable selection matrix including n parallel inputs, coupled to the elastic store to receive the groups of n parallel bits from the elastic store, and n parallel outputs, the selection matrix including means for selecting bits from among more than one of the groups of n parallel bits; and

e) a justification decision circuit (9, 15,

     16), including

i) a phase comparator (16) coupled to the input divider means and the output divider means for comparing phases of the reduced input and output bit clock signals; and

ii) a controller (15) coupled to the phase comparator and responsive to an output signal of the phase comparator and operating at the reduced output bit clock rate, for

A) evaluating the output signal of the phase comparator at a predetermined frame position, to determine whether insertion of a justification bit is necessary; and

B) controlling the selection matrix and the supplying operation from the elastic store based on a result of the evaluation so that any necessary justification bit is inserted at a second predetermined frame position,

so that waiting time jitter is reduced.

2. The circuit of claim 1, wherein the elastic store (4) is an addressable buffer store, and

further comprising a write counter (12) and a read counter (13) for generating write and read addresses, respectively, for the buffer store, the write and read counters being incremented by edges of the reduced input and output bit clock signals, respectively.

3. Circuit as claimed in claim 2,

further comprising a justification monitoring circuit (9) for comparing the addresses of the write and read counters (12,13) and, when the difference between them deviates from a nominal value, applying a signal to the controller (15), and

wherein the controller brings the difference to the nominal value by changing a bit selection of the selection matrix and stopping the read counter.

4. The circuit of claim 1 wherein the selection matrix comprises:

n-1 delay elements, coupled to respective ones of n-1 of the n selection matrix inputs, for delaying signals received from the respective ones of the inputs; and

for selecting a combination of input bits and delayed input bits, n selecting circuits each for selecting a respective bit from among n respective options, each of the n respective options being either a respective delayed bit from one of the delay elements or a respective bit from a respective one of the n inputs, each selecting circuit having a respective output which is a respective one of the n parallel outputs of the selection matrix.

5. The circuit of claim 1, wherein

a) the selection matrix selects bits according to one of a plurality of predetermined patterns of bits from at least two of the groups of n parallel bits, each pattern being identified by a track number, denoted by a variable, s;

and

b) the controller

i) stores a current value of the variable, s,

ii) increments the current value of the variable, s, by unity modulo-n, and thereby specifies selection of a new one of the plurality of predetermined patterns, after insertion of each justification bit, and

iii) causes re-supply of one of the plurality of groups of n parallel bits from the elastic store when the current value of the variable, s, goes from n-1 to zero.

6. The circuit of claim 1, further comprising parallel to serial converter means coupled to the selection matrix and the output divider means for deriving the output signal from the selection matrix under control of the reduced output bit clock signal.

7. The circuit of claim 1 wherein the reduced output bit clock rate is reduced with respect to a bit clock rate of the output bit clock signal by a ratio of 1:

n.

8. The circuit of claim 5 wherein the predetermined frame position is the m^th frame position relative to a reference frame position, where m is an integer chosen along with a second integer k to minimize a value of the expression

9. The circuit of claim 1 wherein n is greater than two.

10. A circuit for adjusting bit rates on input and output signals, which input and output signals comprise bits organized into frames, each frame having a same plurality of frame positions, which frame positions are marked by edges of corresponding input and output bit clock signals, the input signal including justification bits, the input bit clock including gaps, the circuit comprising:

a) input divider means (411,

     414), responsive to the input bit clock signal at a reduced input bit clock rate, which reduced input bit clock rate is reduced at a ratio of 1;

n with respect to a bit clock rate of the input clock signal, where n is an integer greater than 1, and

b) output divider means responsive to the output bit clock signal, for supplying a reduced output bit clock signal at a reduced output bit clock rate;

c) an input serial-to-parallel converter (42) coupled to the input divider means for converting groups of n serial bits of the input signal into groups of n parallel bits;

d) a controllable selection matrix (45) including n parallel inputs, coupled to the input serial-to-parallel converter to receive the groups of n parallel bits from the serial-to-parallel converter, and n parallel outputs, the selection matrix including means for selecting bits from among more than one of the groups of n parallel bits and to remove the justification bits;

e) an elastic store (44), coupled to the controllable selection matrix to receive groups of n parallel bits from the selection matrix at the reduced input bit clock rate including gaps and without justification bits and to supply the groups of n parallel bits at the reduced output bit clock rate; and

f) a justification decision circuit (49,

     415), including

i) a phase comparator (49) coupled to the input divider means and the output divider means for comparing phases of the reduced input and output bit clock signals and recovering a gapless output bit clock signal; and

(ii) a controller (415) responsive to framing and justification indication bits and operating at the reduced output bit clock rate, for

controlling the selection matrix so that any necessary justification bit is deleted so that waiting time jitter is reduced.

11. The circuit of claim 10, further comprising means for deriving the output signal from the elastic store.

12. The circuit of claim 10, wherein the elastic store is an addressable buffer store;

and

further comprising a write counter (412) and a read counter (413) for generating write and read addresses, respectively, for the buffer store, the write and read counters being coupled to the phase comparator and incremented by edges of the reduced input and output bit clock signal, respectively.

13. The circuit of claim 10 wherein the selection matrix comprises:

n-1 delay elements, coupled to respective ones of n-1 of the n selection matrix inputs, for delaying signals received from the respective ones of the inputs; and

for selecting a combination of input bits and delayed input bits, n selecting circuits each for selecting a respective bit from among n respective options, each of the n respective options being either a respective delayed bit from one of the delay elements or a respective bit from a respective one of the n inputs, each selecting circuit having a respective output which is a respective one of the n parallel outputs of the selection matrix.

14. The circuit of claim 10, wherein

a) the selection matrix selects bits according to one of a plurality of predetermined patterns of bits from at least two of the groups of n parallel bits, each pattern being identified by a track number, denoted by an integer variable, s;

and

b) the controller

i) stores a current value of the variable, s,

ii) increments the current value of the variable, s, by unity modulo-n, and thereby specified selection of a new one of the plurality of predetermined patterns, after removal of each justification bit.

15. The circuit of claim 10 wherein the reduced output bit clock rate is reduced with respect to a bit clock rate of the output bit clock signal by a ratio of 1:

n.

16. The circuit of claim 10, wherein n is greater than 2.