Serial interface bus system for transmitting and receiving digital audio information

• US 5,359,626 A
• Filed: 09/02/1992
• Issued: 10/25/1994
• Est. Priority Date: 09/02/1992
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Liu, Clif, Kloker, Kevin L., Wernimont, Thomas L.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): VO, DON NGUYEN
• Application Number:
  US07/939,770
• Time in Patent Office: 783 Days
• Field of Search: 375/7, 375/36, 375/121, 375/106, 375/107, 381/31, 370/58.2, 370/67, 370/85.1, 370/85.9, 370/85.11, 370/110.1
• US Class Current: 375/220
• CPC Class Codes: G11B 20/10527 Audio or video recording; Data buffering arrangements G11B20/12 - G11B20/18 take precedence
• CPC Class Codes: H04B 1/205 with control bus for exchanging commands between units

Abstract

A serial interface bus system for transmitting and receiving a plurality of bus signals which collectively allow communication of data between a digital audio source (12, 22, 24, 26, 56, 82) such as a compact disc and a digital sink (42, 52, 62, 64, 66) such as a digital signal processor. The plurality of bus signals provided by the interface bus system allow many different audio sources and sinks to be used without glue logic. The plurality of bus signals allow multiple transceivers to be configured in a daisy chain (20, 60) wherein a master is selectively chosen to optimize performance of such a system. The daisy chain configuration may be implemented to provide digital data to a wide variety of storage circuits for digital information.

Claims

1. A receiver for providing a plurality of digital data values from a modulated digital audio source to an unmodulated data sink via an interface bus, the interface bus comprising:

a receive output enable conductor for providing a receive enable signal generated by a master controller to the receiver, the receive output enable input selectively enabling the receiver to provide digital data;

a receive system clock conductor for providing a system clock signal from a clock source;

to the receiver, the receive system clock selectively enabled in response to the receive output enable signal;

a plurality of digital data conductors, a first portion of the plurality of digital data values providing digital audio values and a second portion of the plurality of digital data values providing digital non-audio data values, each of the digital audio and non-audio data values being provided in a predetermined format by the plurality of digital data conductors;

a receive input synchronization conductor for providing a receive input synchronization signal from an input synchronization source, the receive input synchronization signal indicating a start of communication of at least one of a first one of the plurality of digital audio data values and a first one of the plurality of digital non-audio data values;

a receive output synchronization conductor for providing a receive output synchronization signal generated by the receiver, the receive output synchronization signal indicating an end of communication of at least one of the first one of the plurality of digital audio data values and the first one of the plurality of digital non-audio data values; and

a frequency lock conductor for providing a lock signal generated by the receiver, the lock signal indicating if the receiver has locked to a frequency of the plurality of digital data values communicated between the modulated digital audio source and the unmodulated data sink.

2. The interface bus of claim 1 wherein each of the digital audio and non-audio data values is provided in a format which is compatible with either an AES-EBU or a CP-340 format.

3. In a data processing system having a plurality of receivers for providing digital data from a plurality of modulated digital audio sources to a plurality of unmodulated serial data sinks via an interface bus, the interface bus comprising:

a receive output enable conductor for providing a receive enable signal from a controller to a first one of the plurality of receivers, the receive output enable input selectively enabling the first one of the plurality of receivers to provide control information necessary to synchronize each of the plurality of receivers to one another;

a receive system clock conductor for providing a system clock signal to each one of the plurality of receivers, the receive system clock generated by the first one of the plurality of receivers;

a plurality of digital data conductors, a first portion of the plurality of digital data values transferring digital audio values and a second portion of the plurality of digital data values transferring digital non-audio data values, each of the digital audio and non-audio data values being transferred in a predetermined format by the plurality of digital data conductors from one of the plurality of receivers;

a receive frame synchronization conductor for communicating a receive frame synchronization signal, the receive frame synchronization signal indicating a start of communication of at least one of a first one of the plurality of digital audio data values and a first one of the plurality of digital non-audio data values, the first one of the plurality of receivers providing the receive frame synchronization signal to each of the remaining portion of the plurality of receivers;

a plurality of receive input synchronization conductors for communicating a plurality of receive input synchronization signals, each one of the plurality of receivers receiving a predetermined one of the plurality of receive input synchronization signals, a second one of the plurality of receivers receiving the receive frame synchronization signal as a corresponding one of the plurality of receive input synchronization signals; and

a plurality of receive output synchronization conductors for communicating a plurality of receive output synchronization signals, the plurality of receive output synchronization signals indicating an end of communication of at least one of the first one of the plurality of digital audio data values and the first one of the plurality of digital non-audio data values, a first receive output synchronization signal corresponding to the second one of the plurality of receivers providing a receive input synchronization signal to a predetermined one of the remaining portion of the plurality of receivers, each of the remaining receive output synchronization signals being provided to a predetermined one of the plurality of receivers.

4. The interface bus of claim 3 wherein the first one of the plurality of receivers is the same as the second one of the plurality of receivers.

5. The interface bus of claim 3 further comprising:

a plurality of frequency lock conductors for providing a plurality of lock signals, each of the plurality of lock signals indicating if a corresponding one of the plurality of receivers has locked to a frequency of the plurality of digital data values communicated between the modulated digital audio source and the unmodulated data sink.

6. The interface bus of claim 5 wherein the receive enable signal is provided to the first one of the plurality of receivers in response to one of the plurality of lock signals.

7. The interface bus of claim 5 wherein only one of the plurality of lock signals is asserted at a predetermined point in time.

8. The interface bus of claim 3 wherein each of the digital audio and non-audio data values is communicated in a format which is compatible with either an AES-EBU or a CP-340 format.

9. In a data processing system having a plurality of transmitters for transmitting digital data from a plurality of unmodulated data sources to a plurality of modulated digital audio sinks via an interface bus, the interface bus comprising:

a transmit output enable conductor for providing a transmit enable signal to a first one of the plurality of transmitters, the transmit output enable signal selectively enabling the first one of the plurality of transmitters to provide control information necessary to synchronize each of the plurality of transmitters to one another;

a transmit system clock conductor for providing a system clock signal generated by the first one of the plurality of transmitters to each one of the plurality of transmitters;

a plurality of digital data conductors, a first portion of the plurality of digital data values transferring digital audio values and a second portion of the plurality of digital data values transferring digital non-audio data values, each of the digital audio and non-audio data values being transferred in a predetermined format from one of the plurality of transmitters by the plurality of digital conductors;

a transmit frame synchronization conductor for communicating a transmit frame synchronization signal, the transmit frame synchronization signal indicating a start of communication of at least one of a first one of the plurality of digital audio data values and a first one of the plurality of digital non-audio data values, the first one of the plurality of transmitters providing the transmit frame synchronization signal;

a plurality of transmit input synchronization conductors for providing a plurality of transmit input synchronization signals, each one of the plurality of transmitters receiving a predetermined one of the plurality of transmit input synchronization signals, a second one of the plurality of transmitters receiving the transmit frame synchronization signal as a corresponding one of the plurality of transmit input synchronization signals; and

a plurality of transmit output synchronization conductors for communicating a plurality of transmit output synchronization signals, the plurality of transmit output synchronization signals indicating an end of communication of at least one of the first one of the plurality of digital audio data values and the first one of the plurality of digital non-audio data values, a first transmit output synchronization signal corresponding to the second one of the plurality of transmitters providing a transmit input synchronization signal to a predetermined one of the remaining portion of the plurality of transmitters, each of the remaining transmit output synchronization signals being provided to a predetermined one of the plurality of transmitters.

10. The interface bus of claim 9 wherein the first one of the plurality of transmitters is the same as the second one of the plurality of transmitters.

11. The interface bus of claim 9 further comprising:

a modulator synchronization output conductor for transferring a modulator synchronization output signal from the first one of the plurality of transmitters, the modulator synchronization output signal asserted by the first one of the plurality of transmitters in response to the transmit enable signal to indicate that the first one of the plurality of transmitters controls synchronization of each of the plurality of transmitters; and

a modulator synchronization input conductor for communicating a modulator synchronization input signal, the modulator synchronization input signal being provided to each of the remaining portion of the plurality of transmitters to indicate that the first one of the plurality of transmitters controls synchronization of each of the plurality of transmitters, the modulator synchronization input signal provided by the modulator synchronization output signal of the first one of the plurality of transmitters.

12. A digital audio processing system having a plurality of transceivers, the plurality of transceivers communicating digital data having an audio portion and a non-audio portion via an interface bus, the interface bus comprising:

an enable conductor for providing an enable signal to a first one of the plurality of transceivers from a controller, the enable input selectively enabling the first one of the plurality of transceivers to either transmit or receive digital data;

a system clock conductor for providing a clock signal to each one of the plurality of transceivers, the clock signal provided by the first one of the plurality of transceivers;

a plurality of digital data conductors, a first portion of the plurality of digital data values either receiving or transmitting digital audio values and a second portion of the plurality of digital data values either receiving or transmitting digital non-audio data values, each of the digital audio and non-audio data values being communicated in a predetermined format from one of the plurality of transceivers;

a frame synchronization conductor for communicating a frame synchronization signal, the frame synchronization signal indicating a start of either receipt or transmission of at least one of a first one of the plurality of digital audio data values and a first one of the plurality of digital non-audio data values, the first one of the plurality of transceivers providing the frame synchronization signal;

a plurality of input synchronization conductors for communicating a plurality of input synchronization signals, each one of the plurality of transceivers receiving a predetermined one of the plurality of input synchronization signals, a second one of the plurality of transceivers receiving the frame synchronization signal as a corresponding one of the plurality of input synchronization signals; and

a plurality of output synchronization conductors for communicating a plurality of output synchronization signals, the plurality of output synchronization signals indicating an end of either receipt or transmission of at least one of the first one of the plurality of digital audio data values and the first one of the plurality of digital non-audio data values, a first output synchronization signal corresponding to the second one of the plurality of transceivers providing an input synchronization signal to a predetermined one of the remaining portion of the plurality of transceivers, each of the remaining output synchronization signals being provided to a predetermined one of the plurality of transceivers.

13. The digital audio processing system of claim 12 further comprising:

a plurality of modulator synchronization conductors for providing a plurality of modulator synchronization signals, the plurality of modulator synchronization signals synchronizing a transmitter portion of each of the plurality of transceivers to a transmitter portion of the first one of the plurality of transceivers during communication of the plurality of digital audio values.

14. The interface bus of claim 12 further comprising:

a plurality of frequency lock conductors for communicating a plurality of lock signals, each of the plurality of lock signals indicating if a corresponding one of the plurality of transceivers has locked to a frequency of the plurality of digital data values communicated between the modulated digital audio source and the unmodulated data sink.

15. The interface bus of claim 14 wherein one of the plurality of lock signals is provided to a first one of the plurality of transceivers in response to the receive enable signal.

16. The interface bus of claim 14 wherein only one of the plurality of lock signals is asserted at a predetermined point in time.

17. The interface bus of claim 12 wherein each of the digital audio and non-audio data values is communicated in a format which is compatible either an AES-EBU or a CP-340 format.

18. The interface bus of claim 12 wherein the plurality of modulator synchronization signals is further comprised of:

a modulator synchronization output conductor for communicating a modulator synchronization output signal, the modulator synchronization output signal asserted by the first one of the plurality of transmitters in response to the transmit enable signal to indicate that the first one of the plurality of transmitters controls synchronization of each of the plurality of transmitters; and

a modulator synchronization input conductor for communicating a modulator synchronization input signal, the modulator synchronization input signal being provided to each of the remaining portion of the plurality of transmitters to indicate that the first one of the plurality of transmitters controls synchronization of each of the plurality of transmitters, the modulator synchronization input signal provided by the modulator synchronization output signal of the first one of the plurality of transmitters.

19. In a digital audio communication system, a method for receiving a plurality of digital audio information values from a plurality of digital audio sources to a digital audio sink, comprising the steps of:

providing a plurality of receivers, each of the receivers receiving the plurality of digital audio information values from a respective one of the plurality of digital audio sources, each one of the plurality of receivers providing the plurality of digital audio information values to the digital audio sink in a predetermined audio serial data bus protocol;

providing a receive output enable signal to a first one of the plurality of receivers, the receive output enable signal enabling the first one of the plurality of receivers to provide a receive system clock signal to each of the plurality of receivers;

providing a receive input synchronization signal from a second one of the plurality of receivers to both the digital audio sink and the first one of the plurality of receivers, the receive input synchronization signal indicating a beginning of a first one of the plurality of digital audio data values transferred from the second one of the plurality of receivers in the audio serial data bus protocol;

transferring the first one of the plurality of digital audio data values from the second one of the plurality of receivers to the digital audio sink upon receipt of the receive input synchronization signal;

providing a first receive output synchronization signal from the second one of the plurality of receivers to a third one of the plurality of receivers, the first receive output synchronization signal indicating an end of the first one of the plurality of digital audio

using the first receive output synchronization signal to enable the third one of the plurality of receivers to transfer a second one of the plurality of digital audio data values in the serial data bus protocol to the digital audio sink. data values; and

20. The interface bus of claim 19 wherein the first one of the plurality of receivers is the same as the second one of the plurality of receivers.

21. The method of claim 19 further comprising the step of:

providing a second receive output synchronization signal from the third one of the plurality of receivers to a fourth one of the plurality of receivers.

22. The method of claim 19 further comprising the step of:

providing a plurality of frequency lock conductors for communicating a plurality of lock signals, each of the plurality of lock signals indicating if a corresponding one of the plurality of transceivers has locked to a frequency of the plurality of digital data values communicated between the modulated digital audio source and the unmodulated data sink.

23. The interface bus of claim 22 wherein only one of the plurality of lock signals is asserted at a predetermined point in time.

24. The interface bus of claim 19 wherein the predetermined audio serial data bus protocol is a format which is compatible with either an AES-EBU or a CP-340 format.

25. In a digital audio communication system, a method for transmitting a plurality of digital audio information values from a digital audio source to a plurality of digital audio sinks, comprising the steps of:

providing a plurality of transmitters for transmitting the plurality of digital audio information values from the digital audio source to a respective one of the plurality of digital audio sinks, each one of the plurality of transmitters receiving the plurality of digital audio information values from the digital audio source in a predetermined audio serial data bus protocol;

providing a transmit output enable signal to a first one of the plurality of transmitters, the transmit output enable signal enabling the first one of the plurality of transmitters to provide a transmit system clock signal to each of the plurality of transmitters;

providing a transmit input synchronization signal from a second one of the plurality of transmitters to both the digital audio source and the first one of the plurality of transmitters, the transmit input synchronization signal indicating a beginning of a first one of the plurality of digital audio data values transferred to the second one of the plurality of transmitters in the audio serial data bus protocol;

transferring the first one of the plurality of digital audio data values to the second one of the plurality of transmitters from the digital audio source upon receipt of the transmit input synchronization signal by the second one of the plurality of transmitters;

providing a first transmit output synchronization signal from the second one of the plurality of transmitters to a third one of the plurality of transmitters, the first transmit output synchronization signal indicating an end of the first one of the plurality of digital audio data values; and

using the first transmit output synchronization signal to enable the third one of the plurality of transmitters to receive a second one of the plurality of digital audio data values in the serial data bus protocol.

26. The method of claim 25 further comprising the step of:

providing a second transmit output synchronization signal from the third one of the plurality of transmitters to a fourth one of the plurality of transmitters.

27. The method of claim 25 further comprising the steps of:

providing a modulator synchronization output conductor for communicating a modulator synchronization output signal, the modulator synchronization output signal asserted by the first one of the plurality of transmitters in response to the transmit enable signal to indicate that the first one of the plurality of transmitters controls synchronization of each of the plurality of transmitters; and

providing a modulator synchronization input conductor for communicating a modulator synchronization input signal, the modulator synchronization input signal being provided to each of the remaining portion of the plurality of transmitters to indicate that the first one of the plurality of transmitters controls synchronization of each of the plurality of transmitters, the modulator synchronization input signal provided by the modulator synchronization output signal of the first one of the plurality of transmitters.