Pyramid processor integrated circuit

• US 5,359,674 A
• Filed: 12/11/1991
• Issued: 10/25/1994
• Est. Priority Date: 12/11/1991
• Status: Expired due to Term

• Current Assignee: Sarnoff Corporation (SRI International, Inc.)
• Original Assignee: David Sarnoff Research Center, Inc.
• Inventors: van der Wal, Gooitzen S.
• Primary Examiner(s): Razavi, Michael T.
• Assistant Examiner(s): CHANG, JON CARLTON
• Application Number:
  US07/805,149
• Time in Patent Office: 1,049 Days
• Field of Search: 382/41, 382/49, 382/43, 382/27, 382/17, 382/54, 382/22, 358/160
• US Class Current: 382/261
• CPC Class Codes: G06T 2200/28 involving image processing hardware
• CPC Class Codes: G06T 2207/20016 Hierarchical, coarse-to-fine, multiscale or multiresolution image processing; Pyramid transform
• CPC Class Codes: G06T 2207/20024 Filtering details
• CPC Class Codes: G06T 5/00 Image enhancement or restoration

Abstract

Multiresolution (pyramid) filtering is useful in image processing. An IC for implementing a variety of multiresolution filters includes a programmable, symmetric, and separable two-dimensional filter. The input signal to the filter can be an input signal applied to the IC or a combination of two such signals. Circuitry in the IC may be programmed to imply pixel values around the edges of the two-dimensional image signals processed by the filter. The filter provides an output signal as well as each of the unfiltered signals from a tapped delay line of a filter that combines successive lines of the image. The IC also includes an arithmetic and logic unit in which the filtered output signal may be combined with an unfiltered input signal or one of the unfiltered tap signals. If the filter is programmed to produce a Gaussian low-pass filtered image, this image, combined with image data from a center one of the filter taps produces a Laplacian function of the original image.

Claims

1. A pyramid processor comprising:

means for receiving a first and a second digital data input signal, each including a data signal component and a timing signal component;

first means, responsive to a first control signal, for selectively combining the respective data signal components of the first and second digital data signals to generate a third digital data signal, and for delaying and selectively combining the respective timing signal components of the first and second digital data signals to compensate for delays incurred in processing the first and second data signals and for combining the compensated timing signal with the third digital data signal;

two-dimensional digital filter means, including first and second component filters, each of said component filters having a respective tapped delay line, for processing the data signal component of the third digital data signal in accordance with a programmed transfer function to produce a first filtered signal;

means, coupled to the two-dimensional filter for delaying the timing signal component of the third digital data signal to compensate for processing delays incurred by the filtering of the third digital data signal;

means coupled to the filter means to receive the filtered signal and an unfiltered signal provided by the tapped delay line of the first component filter and responsive to a second control signal to selectively combine the filtered signal and the unfiltered signal to produce a second filtered signal; and

control means, responsive to a programming signal to generate the first and second control signals.

2. A pyramid processor according to claim 1, wherein:

the first and second component filters are mutually orthogonal.

3. A pyramid processor according to claim 2, wherein:

the two-dimensional digital filter includes first and second sets of programmable coefficient values for the respective first, and second mutually orthogonal component filters; and

the control means is responsive to the programming signal to program the first and second sets of coefficient values.

4. A pyramid processor of claim 3 further comprising:

means for applying an auxiliary digital data input signal; and

means, coupled to the means for applying the auxiliary input signal and to the digital filter means, for combining each sample of the auxiliary signal with L less significant bits of each sample of the filtered signal where each sample of the filtered signal has K bits, K and L being integers and L being greater than K.