Serial access memory

• US 5,361,236 A
• Filed: 12/03/1992
• Issued: 11/01/1994
• Est. Priority Date: 12/19/1991
• Status: Expired due to Term

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Iwakiri, Itsuro
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): NGUYEN, TIEP HUU
• Application Number:
  US07/985,595
• Time in Patent Office: 698 Days
• Field of Search: 365/221, 365/206, 365/189.05
• US Class Current: 365/221
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM

Abstract

A serial access memory includes a pair of bit lines, a plurality of memory cells each coupled to one of the bit lines and a pair of data lines. The serial access memory also includes a sense amplifier drive line, a sense amplifier, data latch circuit, data transfer circuit and a drive capability control circuit. The sense amplifier drive line is coupled to a potential source for supplying a sense amplifier drive signal from the potential source. The sense amplifier is coupled to the bit lines and the sense amplifier drive line for amplifying a difference of electrical potentials appeared on the bit lines in response to the sense amplifier drive signal. The data latch circuit is coupled to the bit lines and the data lines for latching the amplified electrical potentials appeared on the bit lines as data. The data transfer circuit is coupled between the bit lines and the data latch circuit for controlling an electrical connection between the bit lines and the data latch circuit. The drive capability control circuit is coupled between the power potential source and the sense amplifier drive line for controlling an electrical connection between them. The drive capability control circuit controls its drive capability so as to control a sense amplification capability of the sense amplifier.

Claims

1. A memory circuit comprising:

a pair of bit lines;

a data memory circuit having a plurality of memory cells each of which is coupled to a respective one of said bit lines;

a sense amplifier drive line coupled to a potential source for supplying a sense amplifier drive signal from the potential source;

a sense amplifier coupled to said pair of bit lines and said sense amplifier drive line for amplifying a difference of electrical potentials on said pair of bit lines in response to the sense amplifier drive signal, said sense amplifier having a sense amplification capability;

a pair of data lines;

a data latch circuit coupled to said pair of bit lines and said pair of data lines for latching the electrical potentials amplified by said sense amplifier as data, said data latch circuit having a latching capability;

a data transfer circuit coupled between said pair of bit lines and said data latch circuit for controlling an electrical connection between said bit lines and said data latch circuit in response to a data transfer control signal; and

a drive capability control circuit coupled between the potential source and said sense amplifier drive line for controlling an electrical connection between the potential source and sense amplifier drive line so that said drive capability control circuit changes the sense amplification capability of said sense amplifier in response to the data transfer control signal to be larger than the latching capability when said data transfer circuit electrically couples said bit lines and said data latch circuit, said drive capability control circuit including a first transistor coupled between the potential source and said sense amplifier drive line, the first transistor being controlled by the data transfer control signal, and a second transistor coupled in parallel to the first transistor.

2. A memory circuit according to claim 1, further comprising a selection gate circuit coupled between said data latch circuit and said data lines for controlling an electrical connection between the data latch circuit and data lines.

3. A memory circuit according to claim 1, wherein the first transistor has a larger drive capability than a drive capability of the second transistor.

4. The memory circuit of claim 3 wherein said second transistor is coupled to receive and be controlled by a further control signal distinct from the data transfer control signal.

5. A memory circuit having a pair of bit lines for reading data from a plurality of memory cells and a pair of data lines for outputting the read data therefrom, the memory circuit comprising:

a sense amplifier coupled to the bit lines for amplifying a difference of electrical potentials on the bit lines, said sense amplifier receiving a sense amplifier drive signal having a first drive capability;

a data latch circuit coupled to the bit lines and the data lines for latching the electrical potentials amplified by said sense amplifier as data, said data latch circuit receiving a latch drive signal having a second drive capability;

a data transfer circuit coupled between the bit lines and said data latch circuit for controlling an electrical connection between said bit lines and said data latch circuit in response to a data transfer control signal; and

a drive circuit coupled to said sense amplifier for generating the sense amplifier drive signal, said drive circuit setting the first drive capability larger than the second drive capability when the bit lines are coupled to said data latch circuit in response to the data transfer control signal, said drive circuit including a potential source and a first transistor coupled between the potential source and said sense amplifier for controlling an electrical connection between the potential source and said sense amplifier in response to the data transfer control signal controlling the first transistor.

6. A memory circuit according to claim 5, further comprising a selection gate circuit coupled between said data latch circuit and said data lines for controlling an electrical connection between the data latch circuit and data lines.

7. A memory circuit according to claim 6, wherein said drive circuit further includes a second transistor coupled in parallel to the first transistor.

8. A memory circuit according to claim 7, wherein the first transistor has a larger drive capability than a drive capability of the second transistor.

9. The memory circuit of claim 8 wherein said second transistor is coupled to receive and be controlled by a further control signal distinct from the data transfer control signal.

10. A memory circuit having a pair of bit lines for reading data from a plurality of memory cells and a pair of data lines for outputting the read data therefrom, the memory circuit comprising:

a sense amplifier coupled to the bit lines for amplifying a difference of electrical potentials on the bit lines during a first and a second time periods, said sense amplifier receiving a sense amplifier drive signal;

a data latch circuit coupled to the bit lines and the data lines for latching the electrical potentials amplified by said sense amplifier as data, said data latch circuit receiving a latch drive signal having a first drive capability;

a data transfer circuit coupled between the bit lines and said data latch circuit for electrically connecting said bit lines and said data latch circuit in response to a data transfer control signal during the second time period; and

a drive circuit coupled to said sense amplifier for generating the sense amplifier drive signal having a second drive capability during the first time period and a third drive capability that is larger than the first drive capability during the second time period so that a sense amplification capability of said sense amplifier is larger than a latch capability of said data latch circuit during the second time period;

said drive circuit including a potential source and a first transistor coupled between the potential source and said sense amplifier for electrically connecting between the potential source and said sense amplifier during the second time period in response to the data transfer control signal controlling the first transistor.

11. A memory circuit according to claim 10, further comprising a selection gate circuit coupled between said data latch circuit and the data lines for electrically connecting between the data latch circuit and data lines during a third time period.

12. A memory circuit according to claim 10, wherein said drive circuit further includes a second transistor coupled in parallel to the first transistor for electrically connecting between the potential source and said sense amplifier during the first time period.

13. A memory circuit according to claim 12, wherein the first transistor has a larger drive capability than a drive capability of the second transistor.

14. The memory circuit of claim 13 wherein said second transistor is coupled to receive and be controlled by a further control signal distinct from the data transfer control signal.

15. A memory circuit according to claim 10, wherein the second drive capability is equal to or smaller than the third drive capability.