Transmission system for the synchronous digital hierarchy
First Claim
1. An apparatus for transmitting synchronous digital data in a Synchronous Transport Module (STM-N) format in which said data are grouped in containers, wherein said containers include at least a first plurality of said containers each having a respective positive justification location at a predetermined positive location or a respective negative justification location at a predetermined negative location, comprising means for receiving an STM-N signal containing said data in one of said first plurality of containers, means for receiving an output clock signal, and an adaptation circuit for compensating for phase variations of said STM-N signal with respect to said output clock signal,characterized in that said adaptation circuit comprises:
- detecting means for determining whether said one of said first plurality of containers has a positive or has a negative justification location at the corresponding location,a buffer for storing portions of said data of said one of said first plurality of containers at a plurality of addresses,a write address generator, connected to said buffer and synchronized to the received STM-N signal, for forming write addresses at which respective portions of said data of said one of said first plurality of containers are written in said buffer,a read address generator, connected to said buffer and synchronized to said output clock signal, for forming read addresses at which respective portions of said data of said one of said first plurality of containers are read from said buffer,a justification decision circuit, including means for determining differences between said write addresses and said read addresses over a given period of time, and means for determining the mean value of said differences;
said justification decision circuit providing a justification signal responsive to said mean value, said justification signal being indicative of whether or not positive or negative justification is required, andan output circuit for receiving said respective portions read from said buffer, and for providing an output signal based on said respective portions;
responsive to said justification signal being a positive justification signal and said detecting means determining that said first plurality of containers has a positive justification location, for filling said positive location in the one container with at least one justification byte; and
, responsive to said justification signal being a negative justification signal and said detecting means determining that said one of said first plurality of containers has a negative justification location, for filling said negative location in the one container with at least a part of one of said respective portions read from said buffer.
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Accused Products
Abstract
A transmission system for the synchronous digital hierarchy, comprising an adaptation circuit for compensating for phase variations of an STM-N signal. The adaptation circuit (8) comprises a buffer (17, 33), a write address generator (16, 35), a read address generator (18, 44), a justification decision circuit (24, 43) and an output circuit (19, 45), for inserting justification locations for at least one container of the STM-N signal. The buffer is provided for writing and reading the container data. The write address generator is provided for generating write addresses for the data to be written and the read address generator is provided for generating read addresses for the data to be read out. The justification decision circuit is used for forming the mean value of the differences of the addresses of the read and write address generators over a specific period of time and for forming a justification signal as a function of the mean value. The output circuit is provided for generating negative or positive justification locations in the container as a function of the justification signal and for generating an output signal on the basis of the data stored in the buffer.
41 Citations
20 Claims
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1. An apparatus for transmitting synchronous digital data in a Synchronous Transport Module (STM-N) format in which said data are grouped in containers, wherein said containers include at least a first plurality of said containers each having a respective positive justification location at a predetermined positive location or a respective negative justification location at a predetermined negative location, comprising means for receiving an STM-N signal containing said data in one of said first plurality of containers, means for receiving an output clock signal, and an adaptation circuit for compensating for phase variations of said STM-N signal with respect to said output clock signal,
characterized in that said adaptation circuit comprises: -
detecting means for determining whether said one of said first plurality of containers has a positive or has a negative justification location at the corresponding location, a buffer for storing portions of said data of said one of said first plurality of containers at a plurality of addresses, a write address generator, connected to said buffer and synchronized to the received STM-N signal, for forming write addresses at which respective portions of said data of said one of said first plurality of containers are written in said buffer, a read address generator, connected to said buffer and synchronized to said output clock signal, for forming read addresses at which respective portions of said data of said one of said first plurality of containers are read from said buffer, a justification decision circuit, including means for determining differences between said write addresses and said read addresses over a given period of time, and means for determining the mean value of said differences;
said justification decision circuit providing a justification signal responsive to said mean value, said justification signal being indicative of whether or not positive or negative justification is required, andan output circuit for receiving said respective portions read from said buffer, and for providing an output signal based on said respective portions;
responsive to said justification signal being a positive justification signal and said detecting means determining that said first plurality of containers has a positive justification location, for filling said positive location in the one container with at least one justification byte; and
, responsive to said justification signal being a negative justification signal and said detecting means determining that said one of said first plurality of containers has a negative justification location, for filling said negative location in the one container with at least a part of one of said respective portions read from said buffer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An apparatus for transmitting synchronous digital data in a Synchronous Transport Module (STM-N) format in which said data are grouped in containers, wherein said containers include at least a first plurality of said containers each having a respective positive justification location at a predetermined positive location or a respective negative justification location at a predetermined negative location, comprising means for receiving an STM-N signal containing said data in one of said first plurality of containers, means for receiving an output clock signal, and an adaptation circuit for compensating for phase variations of said STM-N signal with respect to said output clock signal,
characterized in that said adaptation circuit comprises: -
detecting means for determining whether said one of said first plurality of containers has a positive or has a negative justification location at the corresponding locations a buffer for storing portions of said data of said one of said first plurality of containers at a plurality of addresses, a write address generator, connected to said buffer and synchronized to the received STM-N signal, for forming write addresses at which respective portions of said data of said one of said first plurality of containers are written in said buffer, a read address generator, connected to said buffer and synchronized to said output clock signal, for forming read addresses at which respective portions of said data of said one of said first plurality of containers are read from said buffer, a justification decision circuit, including means for determining differences between said write addresses and said read addresses over a given period of time, means for setting the difference value between said write address and said read address equal to zero when said buffer is half full, means, including means for accumulating the difference values over said given period of timer for determining the mean value of said differences, means for providing a justification signal responsive to said mean value, said justification signal being indicative of whether or not positive or negative justification is required, and means for multiplying justification signals by a constant factor, and an output circuit for receiving said respective read from said buffer, and for providing an output signal based on said respective portions, wherein, responsive to said justification signal being a positive justification signal and said detecting means determining that said one of said first plurality of containers has a positive justification location, said output circuit fills said positive location in the one container with at least one justification byte; and
, responsive to said justification signal being a negative justification signal and said detecting means determining that said one of said first plurality of containers has a negative justification location, said output circuit fills said negative location in the one container with at least a part of one of said respective portions read from said buffer, andsaid means for accumulating accumulates at least one multiplied value and a difference value. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. An apparatus for transmitting synchronous digital data in a Synchronous Transport Module (STM-N) format in which said data are grouped in frames, each frame comprising at least one container, and each container comprising at least one row, wherein said containers in said frames include at least a first plurality of said containers each having a respective positive justification location at a predetermined positive location or a respective negative justification location at a predetermined negative location, comprising means for receiving an STM-N signal containing said data in one of said first plurality of containers, means for receiving an output clock signal, and an adaptation circuit for compensating for phase variations of said STM-N signal with respect to said output clock signal,
characterized in that said adaptation circuit comprises: -
detecting means for determining whether said one of said first plurality of containers has a positive or has a negative justification location at the corresponding .location, a buffer for storing portions of said data of said one of said first plurality of containers at a plurality of addresses, a write address generator, connected to said buffer and synchronized to the received STM-N signal, for forming write addresses at which respective portions of said data of said one of said first plurality of containers are written in said buffer, a read address generator, connected to said buffer and synchronized to said output clock signal, for forming read addresses at which respective portions of said data of said one of said first plurality of containers are read from said buffer, a justification decision circuit, including means for determining differences between said write addresses and said read addresses over a given period of time corresponding to one row or frame period or a multiple thereof, and means for determining the mean value of said differences;
said justification decision circuit providing a justification signal responsive to said mean value, said justification signal being indicative of whether or not positive or negative justification is required, andan output circuit for receiving said respective portions read from said buffer, and for providing an output signal based on said respective portions;
responsive to said justification signal being a positive justification signal and said detecting means determining that said one of said first plurality of containers has a positive justification location, for filling said positive location in the one container with at least one justification byte; and
, responsive to said justification signal being a negative justification signal and said detecting means determining that said one of said first plurality of containers has a negative justification location, for filling said negative location in the one container with at least a part of one of said respective portions read from said buffer. - View Dependent Claims (17, 18, 19, 20)
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Specification