Method and apparatus for clock distribution and for distributed clock synchronization

• US 5,361,277 A
• Filed: 03/30/1989
• Issued: 11/01/1994
• Est. Priority Date: 04/27/1988
• Status: Expired due to Term

• Current Assignee: Telecommunications Research Laboratories
• Original Assignee: Telecommunications Research Laboratories
• Inventors: Grover, Wayne D.
• Primary Examiner(s): Chin, Stephen
• Application Number:
  US07/331,635
• Time in Patent Office: 2,042 Days
• Field of Search: 375/36, 375/38, 375/106, 375/107, 375/118, 375/10, 455/27, 455/49, 455/51, 328/55, 328/58, 328/72, 370/108, 371/1, 307/262, 307/511
• US Class Current: 375/356
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03K 5/15026 with asynchronously driven series connected output stages
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines

Abstract

A method and apparatus of phase synchronizing a plurality of spatially distributed application modules having synchronizing clocks requiring synchronization, each application module being connected, at a predetermined site nearest the module, to an outgoing path and, at a corresponding site nearest the module, a return path of a pulse reference path, the method comprising the steps of injecting reference pulses at a predetermined frequency into an injection site of the reference path such that the pulses travel along the outgoing path to a remote site and return to the injection site along the return path; determining, for each application module, the time interval for each pulse to travel from the predetermined site to the corresponding site associated with the application module; monitoring, for each application module, the elapsed time interval for each pulse to travel between the predetermined and corresponding sites associated with the application module; producing, for each application module, a local phase reference signal when the elapsed time interval is one-half a last determined one of the time intervals; and synchronizing the clock of each application module with the local phase reference signal.

Claims

1. A clock distribution apparatus for use in providing a common absolute time reference to spatially distributed application modules requiring synchronized clocks, said apparatus comprising:

means for transmitting an outgoing reference signal from a first site to a second site and a return reference signal from said second site to said first site upon arrival of said outgoing reference signal at said second site; and

means at each said application module for detecting an outgoing reference signal and a corresponding return reference signal and producing a local phase reference signal approximately midway through the time interval required for said outgoing reference signal to travel from a signal detecting site at said application module to said second site and said return reference signal to travel from said second site to said signal detecting site.

2. An clock synchronizing apparatus as defined in claim 1, said outgoing and return reference signals having having a maxing frequency given by:

space="preserve" listing-type="equation">f.sub.pulser max =v/2D (3)

where D=the distance from a detecting site to said second site;

v=kc=propagation velocity;

k<

1

c=light propagation velocity in vacuum.

3. An clock synchronizing apparatus as defined in claim 2, further including, at each said application module, means responsive to said local phase reference signal for adjusting the phase of a local clock associated with said application module whereby to provide system-wide phase coherent synchronization of said application modules.

4. A clock synchronizing apparatus as defined in claim 3, further including means defining a reference signal reference path for said outgoing and said return reference signals, said reference path including an outgoing path for transmitting said outgoing reference signal therealong and a return path for transmitting said return reference signal therealong, each said application module having a signal detecting site in said reference path.

5. A clock synchronizing apparatus as defined in claim 4, said reference path comprising a pair of electrical conductors having substantially equal lengths from any point thereon to said second site and being routed as a pair to the location of every application module to be synchronized.

6. A clock synchronizing apparatus as defined in claim 4, said reference path comprising a single electrical conductor routed from said first site to said second site and through to the location of every application module to be synchronized.

7. A clock synchronizing apparatus as defined in claim 4, said reference path being a free-space electromagnetic radiation path.

8. A clock synchronizing apparatus as defined in claim 7, said electromagnetic radiation path including radio, lightwave, infrared or other high frequency electromagnetic radiation paths.

9. A clock synchronizing apparatus as defined in claim 7;

and further including means at each said application module for compensating for non-planar electromagnetic wave fronts.

10. A clock synchronizing apparatus as defined in claim 7 said detecting means including radio antennas optical, infra-red photodiodes, and/or lens assemblies.

11. A clock synchronizing apparatus as defined in claim 3, further including means at said second site for emitting said return reference signal upon receipt of said outgoing reference signal.

12. A clock synchronizing apparatus as defined in claim 3, further including means at said second site for re-transmitting said outgoing reference signal as said return reference signal from said second site towards said first site upon receipt of said outgoing reference signal.

13. A clock synchronizing apparatus as defined in claim 3, said detecting means including interval-halving circuit means.

14. A clock synchronizing apparatus as defined in claim 13, said interval-halving circuit including:

first detector means for producing a output signal upon detecting an outgoing reference signal;

second detector means for producing a second output signal upon detecting a return reference signal;

means responsive to said first and second output signals for determining and storing the time interval between said first and second output signals; and

means responsive to said first output signal for comparing a current time interval with an immediately preceding time interval and producing a reference phase output signal when said current time interval is one half said preceding time interval.

15. A clock synchronizing apparatus as defined in claim 14, said determining and storing means including:

ramp generator means responsive to said first output signal for producing an output linear voltage rise; and

sample and hold gate means responsive to said second output signal for acquiring and storing said output of said ramp generator means.

16. A clock synchronizing apparatus as defined in claim 15, said means for producing said reference phase output signal including a rising edge short pulse generator means.

17. A clock synchronizing apparatus as defined in claim 2, said outgoing and return reference signals being isolated square wave pulses.

18. A clock transmitting apparatus as defined in claim 17, wherein said transmitting means is for producing pulses at an interval greater than the round trip propagation time of said reference signals.

19. A clock synchronizing apparatus as defined in claim 3, said responsive means being a local clock phase lock loop circuit means for locking onto said local phase reference signal.

20. A clock synchronizing apparatus as defined in claim 3, said means responsive to said local phase reference signal comprising a phase lock loop circuit means including a voltage controlled oscillator having an input and an output for producing an oscillator output signal at a frequency and phase determined by a voltage applied to said oscillator input, and divider means for receiving said oscillator output signal for producing POSITIVE and INVERTED output signals;

said detector means including interval-halving circuit means operative to produce a pulse whose duration is equal to said time interval, means for receiving said POSITIVE and INVERTED output signals and said pulse for applying to said input of said voltage controlled oscillator a voltage proportional to the deviation of the transition between said POSITIVE and INVERTED outputs from the center point of said pulse.

21. A clock synchronizing apparatus as defined in claim 20, further including means for maintaining the voltage applied to said oscillator input at a constant value when there is no reference signal flowing between said detecting sites and said second site.

22. A clock synchronizing apparatus as defined in claim 20, said means for receiving said POSITIVE and INVERTED output signals and said predetermined output signal including:

first and second AND gates, each having a pair of inputs and an output, one input of each said AND gate being connected to the output of said detector means, the other input of one of said AND gates for receiving said POSITIVE output and the other input of the other of said AND gates for receiving said INVERTED output; and

first and second switch means having a common output connected to said oscillator input, one of said switch means for receiving the output of one of said AND gates and the other of said switch means for receiving the output of the other of said AND gates.

23. A clock synchronizing apparatus as defined in claim 22, each said switch means being an FET transmission gate.

24. A clock synchronizing apparatus as defined in claim 23, further including means for maintaining the voltage applied to said oscillator input at a constant value when there is no reference pulse flowing between said detecting sites and said second site.

25. A clock synchronizing apparatus as defined in claim 24, said maintaining means being a capacitor.

26. A clock synchronizing apparatus as defined in claim 25, said detector means being a set-reset flip flop.

27. A clock synchronizing apparatus as defined in claim 3, further including means for transmitting a raw clock signal to each said application module.

28. A clock synchronizing apparatus as defined in claim 27, further including means defining a raw clock signal transmission path to each said application module.

29. A clock synchronizing apparatus as defined in claim 28, said means responsive to said local phase reference signal comprising a phase lock loop circuit means including a phase shifter having a first input for receiving said raw clock signal, a second input for receiving said local phase reference signal and an output for delivering a phase aligned clock signal, and divider means adapted to receive said oscillator output signal for producing POSITIVE and INVERTED output signals;

said detector means including interval-halving circuit means operative to produce a pulse whose duration is equal to said time interval, means for receiving said POSITIVE and INVERTED output signals and said pulse for applying to said input of said voltage controlled oscillator a voltage proportional to the deviation of the transition between said POSITIVE and INVERTED outputs from the center point of said pulse.

30. A clock synchronizing apparatus as defined in claim 29, said phase shifter being a digitally controllable, programmable phase shifter.

31. A clock synchronizing apparatus as defined in claim 29, said phase shifter being a continuously variable phase shifter.

32. A clock synchronizing apparatus as defined in claim 29, said means for receiving said POSITIVE and INVERTED output signals and said predetermined output signal including:

first and second AND gates, each having a pair of inputs and an output, one input of each said AND gate being connected to the output of said detector means, the other input of one of said AND gates for receiving said POSITIVE output and the other input of the other of said AND gates for receiving said INVERTED output; and

first and second switch means having a common output connected to said oscillator input, one of said switch means for receiving the output of one of said AND gates and the other of said switch means for receiving the output of the other of said AND gates.

33. A clock synchronizing apparatus as defined in claim 32, each said switch means being an FET transmission gate.

34. A clock synchronizing apparatus as defined in claim 33, said detector means being a set-reset flip flop.

35. A clock synchronizing apparatus as defined in claim 3, said means responsive to said local phase reference signal comprising a phase lock loop circuit means including a voltage controlled oscillator having an input and an output for producing an oscillator clock output signal at a frequency and phase determined by a voltage applied to said oscillator input, and divide-by-N circuit means for receiving said oscillator output signal for delivering a divider output;

said detector means including interval-halving circuit means for controlling the voltage to applied to said oscillator, said interval-halving circuit means comprising;

first and second counter means, each said counter means having a clock input for receiving the output of said oscillator,

said first counter means having a first count output, a first input for receiving said outgoing reference signal and a second input for receiving said divider output and being enabled to count oscillator clock outputs by said outgoing reference signal and being disabled by said divider output;

said second counter means having a second count output, a first input for receiving said divider output and a second input for receiving said return reference signal and being enabled to count oscillator outputs by said divider output and being disabled by said return reference signal;

comparator means for comparing said first and second count outputs producing a first output when said first count output is greater than said second count output and a second output when said second count output is greater than said first count output;

first buffer means responsive to said first comparator output for increasing the voltage applied to said oscillator whereby to increase the frequency of its output; and

second buffer means responsive to said second comparator output for decreasing the voltage applied to said oscillator whereby to decrease the frequency of its output.

36. A clock synchronizing apparatus as defined in claim 3, said detecting means and said responsive means further including:

a fixed frequency oscillator for producing clock signals at a predetermined frequency;

a programmable divider circuit means for receiving said clock signals and having an output and divider first, second and third inputs;

divide-by-N circuit means for receiving said programmable divider circuit means output for delivering a divider output;

first and second counter means, each said counter means having a clock input for receiving said oscillator clock signals;

said first counter means having a first count output, a first input for receiving said outgoing reference signal and a second input for receiving said divider output and being enabled to count oscillator clock outputs by said outgoing reference signal and being disabled by said divider output;

said second counter means having a second count output, a first input for receiving said divider output and a second input for receiving said return reference signal and being enabled to count oscillator clock outputs by said divider output and being disabled by said return reference signal;

comparator means for comparing said first and second count outputs delivering a first output to said first divider input when said first count output is greater than said second count output, a second output to said second divider input when said second count output is greater than said first count output and a third output to said third divider input when said second count output is equal to said first count output;

said programmable divider circuit means being responsive to adjust the phase of its output to provide system-wide phase coherent synchronization of said application modules.

50. A clock synchronizing apparatus as defined in claim 8, further including means at each said application module for compensating for non-planar electromagnetic wave fronts.

51. A clock synchronizing apparatus as defined in claim 8, said detecting means including radio antennas, optical, infra-red photodiodes, and/or lens assemblies.

37. A method of phase synchronizing a plurality of spatially distributed application modules having synchronizing clocks requiring synchronization, said method comprising the steps of:

transmitting an outgoing reference signal from a first site to a second site and a return reference signal from said second site to said first site upon arrival of said outgoing reference signal at said second site; and

detecting an outgoing reference signal and a corresponding return reference signal and producing a local phase reference signal approximately midway through the time interval required for said outgoing reference signal to travel from a signal detecting site at said application module to said second site and said return reference signal to travel from said second site to said signal detecting site.

38. A method as defined in claim 37, wherein said transmitting step includes transmitting a signal at a predetermined frequency wherein the period thereof is greater than the round trip propagation time of said signals.

39. A method as defined in claim 38, said predetermined frequency being less than or equal to

40. A method as defined in claim 37, said predetermined frequency being less than or equal to

41. A method as defined in claim 37, further including the step of regenerating each said reference pulse at said remote site.

42. A method as defined in claim 37, further including the step of terminating and regenerating each said reference signals at the location of each application module extracting synchronism from said signals.

43. A method of phase synchronizing a plurality of spatially distributed application modules having synchronizing clocks requiring synchronization, each said application modules being connected, at a predetermined site nearest said module, to an outgoing path and, at a corresponding site nearest said module, to a return path of a pulse reference path, said method comprising the steps of:

injecting reference pulses at a predetermined frequency into an injection site of said reference path such that said pulses travel along said outgoing path to a remote site and return to said injection site along said return path;

determining, for each said application module, the time interval for each said pulse to travel from said predetermined site to said corresponding site associated with said application module;

monitoring for each said application module the elapsed time interval for each said pulse to travel between said predetermined and corresponding sites associated with said application module;

producing for each said application module a local phase reference signal when said elapsed time interval is one-half a last determined one of said time intervals; and

synchronizing said clock of each said application modules with said local phase reference signal.

44. A method as defined in claim 43, wherein the period of said predetermined frequency is greater than the round trip propagation time of said pulses along said outgoing and return paths of said reference path.

45. A method as defined in claim 43, said predetermined frequency being less than or equal to

46. A method as defined in claim 43, said predetermined frequency being less than or equal to

47. A method as defined in claim 43, further including the step of regenerating each said reference pulse at said remote site.

48. A method as defined in claim 43, further including the step of terminating and regenerating each said reference pulses at the location of each application module extracting synchronism from said reference path.

49. A method as defined in claim 43, said outgoing and return paths having equal lengths from any point thereon to the ends thereof.

52. An electronic system comprising:

a signal source for providing an initial signal;

a plurality of receivers, each having a first and second input lead, each of said receivers requiring the use of an associated one of a plurality of locally generated signals, each of said plurality of locally generated signals corresponding to said initial signal and delayed from said initial signal by a

a signal path having an end for receiving said initial signal, each of said first input leads of said plurality of receivers being connected to said signal path at an associated one of a first plurality of locations along said signal path such that each of said receivers has an associated first propagation delay between said source and said location, such that said first propagation delays are not equal, and each of said second input leads of said plurality of receivers being connected to said signal path at an associated one of a second plurality of locations along said signal path such that each of said receivers has an associated second propagation delay between said source and said location, such that said second propagation delays are not equal; and

a plurality of means, each association with one of said receivers for combining said signals on said first and second input leads in order to generate a locally generated signal corresponding to said initial signal and having a propagation delay from said initial signal which is equal to the average of said first propagation delay and said second propagation delay associated with said receiver.

53. A system as in claim 52 wherein, for each receiver, the sum of the distances between said source and said first and second associated with said receivers is substantially equal to such sum associated with each other receiver.

54. Apparatus for providing a signal comprising:

a first input lead for receiving a first signal corresponding to an initial signal and delayed from said initial signal by a first propagation delay;

a second input lead for receiving a second input signal corresponding to said initial signal and delayed from said initial signal by a second propagation delay;

an output lead for providing a locally generated signal corresponding to said initial signal and delayed from said initial signal by a third propagation delay which is a function of said first and second propagation delays;

a first phase detector for providing a first phase comparison signal indicative of the phase relationship between said first input signal and said locally generated signal;

a second phase detector for providing a second phase comparison signal indicative of the phase relationship between said second input signal and said locally generated signal;

means for combining said phase comparison signal to provide a combined phase comparison signal; and

a voltage controlled oscillator for providing said locally generated signal in response to said combined comparison signal.