Video accelerator and method using system RAM
First Claim
1. A method for storing and accessing information within a computing environment having a first central processing unit (CPU) which is subordinate to a second CPU in accessing a first memory, for which data read and data write operations are required for modifying data stored therein and in which the first CPU has priority access to a second memory, the first CPU being directly connected to the first memory and the second memory by a system bus, and the second CPU being directly connected to the first memory by a video bus, the method comprising the steps of:
- allocating a portion of the second memory for operation as a buffer to the first memory, the portion storing a plurality of blocks of data;
selectively modifying a subset of the plurality of blocks stored in the portion of the second memory responsive to change requirements of the first CPU; and
transferring the modified subset of the plurality of blocks in said portion of the second memory to the first memory directly over the system bus during intervals in which the first memory is available for access by the first CPU.
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Accused Products
Abstract
A computer video display acceleration system and method is disclosed for increasing the speed with which modifications can be made to video memory. This system and method uses a video buffer section in system memory with high priority access by a central processing unit which can use the buffer space to make changes rapidly in the stored video information. Once the changes are completed, the data stored in the buffer is written as a block of data to video memory without requiring additional video memory read cycles.
21 Citations
6 Claims
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1. A method for storing and accessing information within a computing environment having a first central processing unit (CPU) which is subordinate to a second CPU in accessing a first memory, for which data read and data write operations are required for modifying data stored therein and in which the first CPU has priority access to a second memory, the first CPU being directly connected to the first memory and the second memory by a system bus, and the second CPU being directly connected to the first memory by a video bus, the method comprising the steps of:
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allocating a portion of the second memory for operation as a buffer to the first memory, the portion storing a plurality of blocks of data; selectively modifying a subset of the plurality of blocks stored in the portion of the second memory responsive to change requirements of the first CPU; and transferring the modified subset of the plurality of blocks in said portion of the second memory to the first memory directly over the system bus during intervals in which the first memory is available for access by the first CPU. - View Dependent Claims (2, 3, 4)
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5. A computing system comprising:
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a central processing unit having a plurality of input and output ports; a display memory for storing display data blocks selectively transferred from the central processing unit to the display memory; a display processing unit for retrieving display data stored in the display memory with higher access priority to the display memory than the central processing unit; a system memory including addressable locations for storing a plurality of display data blocks, and addressable locations for the storage of block change data relating to addresses of a subset of the plurality of blocks, the subset representing ones of said blocks having been most recently modified; a system bus directly connecting the central processing unit, the display memory, and the system memory; and a video bus directly connecting the display memory and the display processing unit;
said central processing unit accelerating display changes by storing a copy of the display data in the system memory, by modifying data in the system memory and updating said block change data in response to processing instructions, and by transferring the subset of data blocks from the system memory to the display memory during intervals in which the display memory is available for acces by the central processing unit. - View Dependent Claims (6)
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Specification