Plasma-enhanced CVD process using TEOS for depositing silicon oxide

• US 5,362,526 A
• Filed: 01/23/1991
• Issued: 11/08/1994
• Est. Priority Date: 12/19/1986
• Status: Expired due to Term

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Maydan, Dan, White, John M., Umotoy, Salvador P., Collins, Kenneth S., Law, Kam S., Perlov, Ilya, Leung, Cissy, Adamik, John A., Wang, David N.
• Primary Examiner(s): PIANALTO, BERNARD D
• Application Number:
  US07/645,999
• Time in Patent Office: 1,385 Days
• Field of Search: 427/38, 427/58, 427/579, 427/573, 427/574, 427/294, 427/314, 427/237, 427/238, 427/255.3
• US Class Current: 427/573
• CPC Class Codes: C23C 16/402 Silicon dioxide
• CPC Class Codes: C23C 16/455 characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
• CPC Class Codes: C23C 16/45521 the gas, other than thermal contact gas, being introduced the rear of the substrate to flow around its periphery
• CPC Class Codes: C23C 16/45565 Shower nozzles
• CPC Class Codes: C23C 16/5096 Flat-bed apparatus
• CPC Class Codes: C23C 16/54 Apparatus specially adapted for continuous coating
• CPC Class Codes: H01J 37/32082 Radio frequency generated discharge H01J37/32357, H01J37/32366, H01J37/32394 and H01J37/32403 take precedence
• CPC Class Codes: H01J 37/3244 Gas supply means
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02129 the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
• CPC Class Codes: H01L 21/02131 the material being halogen doped silicon oxides, e.g. FSG
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence

Abstract

A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

Claims

1. A TEOS based, plasma enhanced, CVD process for depositing a film of a silicon oxide having improved step coverage onto a surface of a semiconductor wafer having small dimension stepped topographies, such wafer being positioned inside a vacuum chamber to receive the silicon oxide, comprising the steps of:

heating the wafer to a temperature in the range of about 200 degrees C. to 500 degrees C.;

pressurizing the chamber to between about 1 to 50 torr;

dispensing toward the wafer a gas mixture which includes an effective amount of tetraethylorthosilicate ("TEOS") from a generally planar dispensing area which is close to and substantially parallel to the wafer surface, the gas mixture being dispensed uniformly over the wafer surface; and

applying an effective amount of RF power between the dispensing area and the wafer, to excite the gas mixture into a plasma state in a region between the wafer and the dispensing area;

so that a layer of silicon oxide is deposited onto the wafer at a deposition rate greater than 400 angstroms per minute, said deposited silicon oxide layer film quality and step coverage adequate for VLSI semiconductor fabrication.

2. The process according to claim 1, wherein the step of applying further comprises confining the plasma to a region corresponding to a single wafer.

3. The process according to claim 1, wherein the surface area of the planar dispensing area is approximately equal to or greater than the surface area of said wafer surface.

4. The process according to claim 1,

wherein the dispensing step further comprises dispensing the gas mixture toward the wafer through a plurality of openings in an electrically conductive electrode, said dispensing electrode having a planar surface containing said openings which faces the wafer and which is substantially coextensive with said planar dispensing area;

and

wherein the step of applying RF power further comprises electrically connecting a source of RF power to the dispensing electrode.

5. The process according to claim 4, wherein the step of applying RF power further comprises electrically connecting said source of RF power between the dispensing electrode and the wafer.

6. The process according to claim 1, wherein the step of applying RF power further comprises the steps of mounting the wafer on a pedestal which contains an electrically conductive electrode, and electrically connecting a source of RF power to the pedestal electrode.

7. The process according to claim 1, wherein the step of applying RF power further comprises the RF power being applied to said thin region at a power density of about 1 watt/cm².

8. The process according to claim 1, wherein the step of applying RF power is performed with said RF power having a frequency of approximately 13 MHz.

9. The process according to claim 1, wherein, during the dispensing step and the applying step, the wafer surface is positioned a short distance from the planar dispensing area, said short distance being much less than the diameter of the wafer.

10. The process according to claim 9, further comprising, prior to the dispensing step and the applying step, the steps of:

transporting the wafer to a moveable pedestal; and

moving the pedestal so that the wafer surface is substantially parallel to, and is said short distance from, the planar dispensing area.

11. The process according to claim 1, further including the step of providing oxygen to the gas mixture at an oxygen flow rate between about 100 and 1000 sccm such that the total flow rate of the gas mixture is between about 200 and 2500 sccm.

12. The process according to claim 1, wherein the deposit of the silicon oxide onto the wafer is at a rate substantially greater than 400 angstroms per minute.

13. The process according to claim 1, wherein the deposit of the silicon oxide onto the wafer is at a rate greater than or equal to about 5000 angstroms per minute.

14. The process according to claim 1, wherein the dispensing step further includes the step of gasifying liquid TEOS.

15. The process according to claim 1, wherein the pressurizing step comprises pressurizing the chamber to between about 8 to 12 torr.