Method of making vertical DRAM cross point memory cell

• US 5,362,665 A
• Filed: 02/14/1994
• Issued: 11/08/1994
• Est. Priority Date: 02/14/1994
• Status: Expired due to Term

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Lu, Chih-Yuan
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US08/194,736
• Time in Patent Office: 267 Days
• Field of Search: 437/47, 437/48, 437/52, 437/60, 437/919, 437/203, 437/26, 257/302, 257/303
• US Class Current: 438/253
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

A pattern of field oxide isolation in a silicon substrate is provided wherein there are a pattern of openings to the silicon substrate. A pattern is formed of buried bit lines and a pattern of lines of holes with a hole located within each of the openings to said silicon substrate which lines of holes and buried bit lines are perpendicular to one another and which the lines cross at the planned locations of the vertical DRAM cell at the pattern of openings to the silicon substrate. A gate dielectric is formed on the surfaces of the holes. A doped polysilicon layer is formed in and over the holes. The doped polysilicon layer is etched to form the gate electrode and word lines which are perpendicular to the pattern of buried bit lines. The source/drain elements are formed surrounding the gate electrode in the surface of the substrate by ion implantation using the field oxide and gate electrode and word lines as the mask. The buried bit lines form common and additional source/drain elements. An insulating layer is provided over the pattern of field oxide insulation, word lines and openings to the source/drain elements surrounding the gate electrode. An opening is formed through the insulating layer surrounding the gate electrode. A capacitor is formed in and over the opening through the insulating layer.

Claims

1. The method for fabricating a vertical DRAM cell which includes a field effect transistor having a Sate electrode and source/drain elements and a capacitor comprising:

providing a pattern of field oxide isolation in a silicon substrate wherein there are a pattern of openings to the silicon substrate, and a pattern of buried bit lines and a pattern of lines of holes with a hole located within each of said openings to said silicon substrate which lines of holes and buried bit lines are perpendicular to one another and which said lines cross at the planned locations of said vertical DRAM cell at said pattern of openings to the silicon substrate;

forming a gate dielectric on the surfaces of said holes;

forming a doped polysilicon layer in and over said holes so that it covers said gate dielectric;

etching said doped polysilicon layer to form said Sate electrode and word lines which are perpendicular to said pattern of buried bit lines;

forming said source/drain elements surrounding said Sate electrode in the surface of said substrate by ion implantation using the field oxide and gate electrode and word lines as the mask;

wherein said buried bit lines form common and additional said source/drain elements;

providing an insulating layer over said pattern of field oxide insulation, said word lines and openings to said source/drain elements surrounding said gate electrode;

forming an opening through said insulating layer surrounding said gate electrode; and

forming a capacitor in and over said opening through said insulating layer.

2. The method of claim 1 wherein said silicon substrate comprises a base substrate and an epitaxial silicon layer formed over said base substrate, and said pattern of buried bit lines are formed in said base substrate.

3. The method of claim 2 wherein said base substrate is composed of monocrystalline silicon.

4. The method of claim 1 wherein said pattern of buried bit lines are formed below the surface of said silicon substrate by high energy ion implantation through a mask.

5. The method of claim 4 wherein said high energy ion implantation uses a energy of between about 80 KEV to MEV and a dopant concentration of about 2 E 14 to 2 E 16 atoms/cm².

6. The method of claim 1 wherein the dopant concentration level of said buried bit lines is between about 1 E 19 to 1 E 21 atoms/cm³.

7. The method of claim 1 wherein the size of said pattern of openings to said silicon substrate is between about 0.3 to 1.0 micrometers.

8. The method of claim 1 wherein said hole located within each of said openings to said silicon substrate is centrally located therein, the hole reaches to said buried bit lines, and has a diameter of between about 0.1 to 0.7 micrometers.

9. The method of claim 8 wherein said depth of said hole is between about 0.1 to 0.7 micrometers.

10. The method of claim 1 wherein said source/drain elements surrounding said gate electrode in the surface of said substrate and said buried bit lines common and source/drain elements cooperate with said gate electrode to form said field effect transistor of said vertical DRAM cell.

11. The method of claim 10 wherein said capacitor is connected to said field effect transistor to form said vertical DRAM cell.

12. The method of claim 1 wherein said capacitor is formed by depositing a polysilicon node plate layer over and into said opening and in electrical contact with said source/drain elements, forming a capacitor dielectric layer thereover and forming a polysilicon ground plate layer over said dielectric layer.

13. The method of claim 12 wherein said capacitor wherein said polysilicon node plate layer is formed with a rippled pattern so as to increase the effective surface area of said node plate layer.

14. The method for fabricating a vertical DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements and a capacitor comprising:

providing a base substrate;

forming a pattern of buried bit lines in said base substrate, and forming a silicon substrate over said base substrate by epitaxial growth;

forming a pattern of field oxide isolation in said silicon substrate wherein there are a pattern of openings to the silicon substrate;

forming a pattern of lines of holes with a hole located within each of said openings to said silicon substrate which lines of holes and said buried bit lines are perpendicular to one another and which said lines cross at the planned locations of said vertical DRAM cell at said pattern of openings to the silicon substrate;

forming a gate dielectric on the surfaces of said holes;

forming a doped polysilicon layer in and over said holes so that it covers said gate dielectric;

etching said doped polysilicon layer to form said gate electrode and word lines which are perpendicular to said pattern of buried bit lines;

forming said source/drain elements surrounding said gate electrode in the surface of said substrate by ion implantation using the field oxide and gate electrode and word lines as the mask;

wherein said buried bit lines form common and additional said source/drain elements;

providing an insulating layer over said pattern of field oxide insulation, said word lines and openings to said source/drain elements surrounding said gate electrode;

forming an opening through said insulating layer surrounding said gate electrode; and

forming a capacitor in and over said opening through said insulating layer.

15. The method of claim 14 wherein the thickness of said epitaxial layer is between about 0.1 to 0.8 micrometers.

16. The method of claim 14 wherein the dopant concentration level of said buried bit lines is between about 1 E 19 to 1 E 21 atoms/cm³.

17. The method of claim 14 wherein the size of said pattern of openings to said silicon substrate is between about 0.3 to 1.0 micrometers.

18. The method of claim 14 wherein said hole located within each of said openings to said silicon substrate is centrally located therein, the hole reaches to said buried bit lines, and has a diameter of between about 0.1 to 0.7 micrometers.

19. The method of claim 18 wherein said depth of said hole is between about 0.1 to 0.7 micrometers.

20. The method of claim 14 wherein said source/drain elements surrounding said gate electrode in the surface of said substrate and said buried bit lines common and source/drain elements cooperate with said gate electrode to form said field effect transistor of said vertical DRAM cell.

21. The method of claim 20 wherein said capacitor is connected to said field effect transistor to form said vertical DRAM cell.

22. The method of claim 14 wherein said capacitor is formed by depositing a polysilicon node plate layer over and into said opening and in electrical contact with said source/drain elements, forming a capacitor dielectric layer thereover and forming a polysilicon ground plate layer over said dielectric layer.

23. The method of claim 22 wherein said capacitor wherein said polysilicon node plate layer is formed with a rippled pattern so as to increase the effective surface area of said node plate layer.