Method of making vertical DRAM cross point memory cell
First Claim
1. The method for fabricating a vertical DRAM cell which includes a field effect transistor having a Sate electrode and source/drain elements and a capacitor comprising:
- providing a pattern of field oxide isolation in a silicon substrate wherein there are a pattern of openings to the silicon substrate, and a pattern of buried bit lines and a pattern of lines of holes with a hole located within each of said openings to said silicon substrate which lines of holes and buried bit lines are perpendicular to one another and which said lines cross at the planned locations of said vertical DRAM cell at said pattern of openings to the silicon substrate;
forming a gate dielectric on the surfaces of said holes;
forming a doped polysilicon layer in and over said holes so that it covers said gate dielectric;
etching said doped polysilicon layer to form said Sate electrode and word lines which are perpendicular to said pattern of buried bit lines;
forming said source/drain elements surrounding said Sate electrode in the surface of said substrate by ion implantation using the field oxide and gate electrode and word lines as the mask;
wherein said buried bit lines form common and additional said source/drain elements;
providing an insulating layer over said pattern of field oxide insulation, said word lines and openings to said source/drain elements surrounding said gate electrode;
forming an opening through said insulating layer surrounding said gate electrode; and
forming a capacitor in and over said opening through said insulating layer.
1 Assignment
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Accused Products
Abstract
A pattern of field oxide isolation in a silicon substrate is provided wherein there are a pattern of openings to the silicon substrate. A pattern is formed of buried bit lines and a pattern of lines of holes with a hole located within each of the openings to said silicon substrate which lines of holes and buried bit lines are perpendicular to one another and which the lines cross at the planned locations of the vertical DRAM cell at the pattern of openings to the silicon substrate. A gate dielectric is formed on the surfaces of the holes. A doped polysilicon layer is formed in and over the holes. The doped polysilicon layer is etched to form the gate electrode and word lines which are perpendicular to the pattern of buried bit lines. The source/drain elements are formed surrounding the gate electrode in the surface of the substrate by ion implantation using the field oxide and gate electrode and word lines as the mask. The buried bit lines form common and additional source/drain elements. An insulating layer is provided over the pattern of field oxide insulation, word lines and openings to the source/drain elements surrounding the gate electrode. An opening is formed through the insulating layer surrounding the gate electrode. A capacitor is formed in and over the opening through the insulating layer.
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Citations
23 Claims
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1. The method for fabricating a vertical DRAM cell which includes a field effect transistor having a Sate electrode and source/drain elements and a capacitor comprising:
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providing a pattern of field oxide isolation in a silicon substrate wherein there are a pattern of openings to the silicon substrate, and a pattern of buried bit lines and a pattern of lines of holes with a hole located within each of said openings to said silicon substrate which lines of holes and buried bit lines are perpendicular to one another and which said lines cross at the planned locations of said vertical DRAM cell at said pattern of openings to the silicon substrate; forming a gate dielectric on the surfaces of said holes; forming a doped polysilicon layer in and over said holes so that it covers said gate dielectric; etching said doped polysilicon layer to form said Sate electrode and word lines which are perpendicular to said pattern of buried bit lines; forming said source/drain elements surrounding said Sate electrode in the surface of said substrate by ion implantation using the field oxide and gate electrode and word lines as the mask; wherein said buried bit lines form common and additional said source/drain elements; providing an insulating layer over said pattern of field oxide insulation, said word lines and openings to said source/drain elements surrounding said gate electrode; forming an opening through said insulating layer surrounding said gate electrode; and forming a capacitor in and over said opening through said insulating layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. The method for fabricating a vertical DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements and a capacitor comprising:
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providing a base substrate; forming a pattern of buried bit lines in said base substrate, and forming a silicon substrate over said base substrate by epitaxial growth; forming a pattern of field oxide isolation in said silicon substrate wherein there are a pattern of openings to the silicon substrate; forming a pattern of lines of holes with a hole located within each of said openings to said silicon substrate which lines of holes and said buried bit lines are perpendicular to one another and which said lines cross at the planned locations of said vertical DRAM cell at said pattern of openings to the silicon substrate; forming a gate dielectric on the surfaces of said holes; forming a doped polysilicon layer in and over said holes so that it covers said gate dielectric; etching said doped polysilicon layer to form said gate electrode and word lines which are perpendicular to said pattern of buried bit lines; forming said source/drain elements surrounding said gate electrode in the surface of said substrate by ion implantation using the field oxide and gate electrode and word lines as the mask; wherein said buried bit lines form common and additional said source/drain elements; providing an insulating layer over said pattern of field oxide insulation, said word lines and openings to said source/drain elements surrounding said gate electrode; forming an opening through said insulating layer surrounding said gate electrode; and forming a capacitor in and over said opening through said insulating layer. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23)
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Specification