SOI transistor with improved source-high performance

• US 5,362,979 A
• Filed: 08/10/1993
• Issued: 11/08/1994
• Est. Priority Date: 02/01/1991
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Inventors: Merchant, Steven L.
• Primary Examiner(s): Crane, Sara W.
• Assistant Examiner(s): Monin, Jr., Donald L.
• Application Number:
  US08/105,213
• Time in Patent Office: 455 Days
• Field of Search: 257/347, 257/348, 257/350, 257/66, 257/401, 257/409, 257/57, 257/349, 257/365, 257/340
• US Class Current: 257/340
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical
• CPC Class Codes: H01L 29/861 Diodes

Abstract

The present application is directed to an improved arrangement for a thin silicon SOI transistor having improved source-high performance especially for bridge type circuits. This structure prevents forward current saturation during such source-high operations, and is made by forming the laterally extending silicon layer with a region of thinner thickness over 1/3 to 2/3 of the length of the drift region, or the lateral linear doping region. The field plate is formed with a separation from the gate electrode, and only extends over the thinned portion of the drift region. The gate electrode and field plate are short-circuited by a metal interconnect.

Claims

1. A thin film SOI device having improved source-high performance characteristics comprising the structure of a buried oxide layer;

a layer of silicon on said buried oxide layer, said layer of silicon having a laterally extending region of both a first thickness and a second smaller thickness;

a second oxide layer on said layer of silicon;

a gate electrode above a a portion of said first thickness of said layer of silicon;

a drain region laterally adjacent to said second smaller thickness of said layer of silicon;

a source region laterally separated from said gate electrode;

a field plate separate from said gate electrode and extending laterally over said second smaller thickness of said layer of silicon, and means for short-circuiting said gate electrode and said field plate.

2. A thin film SOI device according to claim 1, wherein said second smaller thickness extends over about 1/3 to 2/3 of said laterally extending region of said layer of silicon.

3. A thin film SOI device according to claim 1, wherein said second smaller thickness has a thickness of 0.1-0.4 μ

m.

4. A thin film SOI device according to claim 1, wherein said first thickness of said layer of silicon is about 1-2 μ

m.

5. A thin film SOI device according to claim 1, wherein both said gate electrode and said field plate are polysilicon, and said means for short-circuiting is conductive metal extending over said second oxide layer.