Transconductance amplifier

• US 5,363,059 A
• Filed: 06/17/1993
• Issued: 11/08/1994
• Est. Priority Date: 06/17/1993
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Thiel, Fran L.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US08/078,385
• Time in Patent Office: 509 Days
• Field of Search: 330/253, 330/255, 330/257
• US Class Current: 330/253
• CPC Class Codes: H03F 3/3001 with field-effect transistors
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

A transconductance amplifier 12 includes a differential input connected to a current amplification network and a source follower output connected to the current amplification network. The CMOS topology coupled with the source follower type output provide an extremely low current, low output impedance transconductance amplifier. The source follower output includes low threshold voltage transistors that also provide an extremely large output voltage swing.

Claims

1. A low quiescent current, high output swing, low output impedance transconductance amplifier, comprising:

a first PMOS transistor having a source, a gate forming a first input, and a drain;

a second PMOS transistor having a source connected to the source of the first PMOS transistor, a gate forming a second input, and a drain;

a third PMOS transistor having a source connected to a first voltage source, a gate, and a drain connected to the source of the first PMOS transistor;

a fourth PMOS transistor having a source connected to the first voltage source, a gate connected to the gate of the third PMOS transistor, and a drain connected to its gate;

a fifth PMOS transistor having a source connected to the first voltage source, a gate connected to a first disable input, and a drain connected to the gate of the third PMOS transistor;

a sixth PMOS transistor having a source connected to the first voltage source, a gate, and a drain connected to its gate;

a seventh PMOS transistor having a source connected to the first voltage source, a gate connected to the gate of the sixth PMOS transistor, and a drain;

an eighth PMOS transistor having a source connected to the first voltage source, a gate connected to the first disable input, and a drain connected to the gate of the sixth PMOS transistor;

a ninth PMOS transistor having a source connected to the first voltage source, a gate connected to the first disable input, and a drain;

a tenth PMOS transistor having a source, a gate connected to the drain of the ninth PMOS transistor, and a drain connected to its gate;

an eleventh PMOS transistor having a source, a gate connected to the gate of the tenth PMOS transistor, and a drain connected to a second voltage source;

a first NMOS transistor having a drain connected to a current source, a gate connected to its drain, and a source connected to the second voltage source;

a second NMOS transistor having a drain connected to the gate of the first NMOS transistor, a gate connected to a second disable input, and a source connected to the second voltage source;

a third NMOS transistor having a drain connected to the drain of the fourth PMOS transistor, a gate connected to the gate of the first NMOS transistor, and a source connected to the second voltage source;

a fourth NMOS transistor having a drain connected to the drain of the first PMOS transistor, a gate connected to its drain, and a source;

a fifth NMOS transistor having a drain connected to the drain of the sixth PMOS transistor, a gate connected to the gate of the fourth NMOS transistor, and a source;

a sixth NMOS transistor having a drain connected to the drain of the second PMOS transistor, a gate connected to its drain, and a source;

a seventh NMOS transistor having a drain connected to the drain of the tenth PMOS transistor, a gate connected to the gate of the sixth NMOS transistor, and a source;

an eighth NMOS transistor having a drain connected to the gate of the sixth NMOS transistor, a gate connected to the second disable input, and a source connected to the second voltage source;

a ninth NMOS transistor having a drain connected to the drain of the seventh PMOS transistor, a gate connected to its drain, and a source connected to the source of the tenth PMOS transistor;

a tenth NMOS transistor having a drain connected to the first voltage source, a gate connected to the gate of the ninth NMOS transistor, and a source connected to the source of the eleventh PMOS transistor and forming an output of the amplifier;

a capacitance having a first terminal connected to the drain of the second PMOS transistor and a second terminal connected to the output of the amplifier;

a first resistance having a first terminal connected to the source of the fourth NMOS transistor and a second terminal connected to the second voltage source;

a second resistance having a first terminal connected to the source of the fifth NMOS transistor and a second terminal connected to the second voltage source;

a third resistance having a first terminal connected to the source of the sixth NMOS transistor and a second terminal connected to the second voltage source; and

a fourth resistance having a first terminal connected to the source of the seventh NMOS transistor and a second terminal connected to the second voltage source.

2. The amplifier of claim 1 wherein the first NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the ninth NMOS transistor, the fourth PMOS transistor, the sixth PMOS transistor, and the tenth PMOS transistor have a (W/L) size ratio of one, the third NMOS transistor, the seventh NMOS transistor, and the seventh PMOS transistor have a (W/L) size ratio of two, the third PMOS transistor has a (W/L) size ratio of four, and the tenth NMOS transistor and the eleventh PMOS transistor have a (W/L) size ratio of five.

3. The amplifier of claim 1 wherein the tenth NMOS transistor has a gate to source threshold voltage less than 0.2V and the eleventh PMOS transistor has a gate to source threshold voltage greater than -0.2V.